JPS64814A - Complementary signal output circuit - Google Patents

Complementary signal output circuit

Info

Publication number
JPS64814A
JPS64814A JP62246767A JP24676787A JPS64814A JP S64814 A JPS64814 A JP S64814A JP 62246767 A JP62246767 A JP 62246767A JP 24676787 A JP24676787 A JP 24676787A JP S64814 A JPS64814 A JP S64814A
Authority
JP
Japan
Prior art keywords
signal
output
high level
low level
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62246767A
Other languages
English (en)
Japanese (ja)
Other versions
JPH01814A (ja
JPH0434327B2 (enrdf_load_stackoverflow
Inventor
Hiroyuki Hara
Shoji Ueno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62246767A priority Critical patent/JPS64814A/ja
Priority to US07/230,549 priority patent/US4950920A/en
Priority to EP88307474A priority patent/EP0310232B1/en
Priority to DE8888307474T priority patent/DE3875216T2/de
Priority to KR1019880010532A priority patent/KR920000837B1/ko
Publication of JPH01814A publication Critical patent/JPH01814A/ja
Publication of JPS64814A publication Critical patent/JPS64814A/ja
Publication of JPH0434327B2 publication Critical patent/JPH0434327B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
JP62246767A 1987-03-24 1987-09-30 Complementary signal output circuit Granted JPS64814A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP62246767A JPS64814A (en) 1987-03-24 1987-09-30 Complementary signal output circuit
US07/230,549 US4950920A (en) 1987-09-30 1988-08-10 Complementary signal output circuit with reduced skew
EP88307474A EP0310232B1 (en) 1987-09-30 1988-08-11 Complementary signal output circuit
DE8888307474T DE3875216T2 (de) 1987-09-30 1988-08-11 Komplementaersignal-ausgangsschaltung.
KR1019880010532A KR920000837B1 (ko) 1987-09-30 1988-08-19 상보신호출력회로

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP62-67963 1987-03-24
JP6796387 1987-03-24
JP62246767A JPS64814A (en) 1987-03-24 1987-09-30 Complementary signal output circuit

Publications (3)

Publication Number Publication Date
JPH01814A JPH01814A (ja) 1989-01-05
JPS64814A true JPS64814A (en) 1989-01-05
JPH0434327B2 JPH0434327B2 (enrdf_load_stackoverflow) 1992-06-05

Family

ID=26409201

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62246767A Granted JPS64814A (en) 1987-03-24 1987-09-30 Complementary signal output circuit

Country Status (1)

Country Link
JP (1) JPS64814A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003536201A (ja) * 2000-06-22 2003-12-02 マイクロン・テクノロジー・インコーポレーテッド 均衡が取れたデュアルエッジでトリガーされたデータビットシフトの回路および方法
WO2014175299A1 (ja) * 2013-04-26 2014-10-30 株式会社村田製作所 スイッチング電源装置用制御回路

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003536201A (ja) * 2000-06-22 2003-12-02 マイクロン・テクノロジー・インコーポレーテッド 均衡が取れたデュアルエッジでトリガーされたデータビットシフトの回路および方法
WO2014175299A1 (ja) * 2013-04-26 2014-10-30 株式会社村田製作所 スイッチング電源装置用制御回路

Also Published As

Publication number Publication date
JPH0434327B2 (enrdf_load_stackoverflow) 1992-06-05

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