JPS6481237A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6481237A JPS6481237A JP23832887A JP23832887A JPS6481237A JP S6481237 A JPS6481237 A JP S6481237A JP 23832887 A JP23832887 A JP 23832887A JP 23832887 A JP23832887 A JP 23832887A JP S6481237 A JPS6481237 A JP S6481237A
- Authority
- JP
- Japan
- Prior art keywords
- insulation resin
- substrate
- semiconductor chip
- resin
- circuiting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/10165—Alignment aids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/8114—Guiding structures outside the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
Abstract
PURPOSE:To suppress open-circuiting between electrodes due to release between resin and substrate or between semiconductor chips by including gap control agent within insulation resin to relax stress of semiconductor chip after curing of insulation resin. CONSTITUTION:By providing a protrusion electrode 3 at either wiring of a semiconductor chip 1 or that of a substrate 6, for example at a wiring 5 of the substrate 6, a gap control agent 2 is included within an insulation resin 4 in a semiconductor device bonded by the insulation resin 4. It allows a uniform height within the semiconductor chip to be maintained and load applied to each protrusion electrode to be held at a constant level for preventing open- circuiting between electrodes.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23832887A JPS6481237A (en) | 1987-09-22 | 1987-09-22 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23832887A JPS6481237A (en) | 1987-09-22 | 1987-09-22 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6481237A true JPS6481237A (en) | 1989-03-27 |
Family
ID=17028574
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23832887A Pending JPS6481237A (en) | 1987-09-22 | 1987-09-22 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6481237A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02127060U (en) * | 1989-03-30 | 1990-10-19 | ||
US5700715A (en) * | 1994-06-14 | 1997-12-23 | Lsi Logic Corporation | Process for mounting a semiconductor device to a circuit substrate |
JP2000036502A (en) * | 1998-07-17 | 2000-02-02 | Sony Corp | Bonding material and bonded object |
-
1987
- 1987-09-22 JP JP23832887A patent/JPS6481237A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02127060U (en) * | 1989-03-30 | 1990-10-19 | ||
US5700715A (en) * | 1994-06-14 | 1997-12-23 | Lsi Logic Corporation | Process for mounting a semiconductor device to a circuit substrate |
JP2000036502A (en) * | 1998-07-17 | 2000-02-02 | Sony Corp | Bonding material and bonded object |
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