JPS64805A - Fet multiplier - Google Patents

Fet multiplier

Info

Publication number
JPS64805A
JPS64805A JP15587287A JP15587287A JPS64805A JP S64805 A JPS64805 A JP S64805A JP 15587287 A JP15587287 A JP 15587287A JP 15587287 A JP15587287 A JP 15587287A JP S64805 A JPS64805 A JP S64805A
Authority
JP
Japan
Prior art keywords
gate
fet
source
resistance
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15587287A
Other languages
Japanese (ja)
Other versions
JPH01805A (en
Inventor
Hiroshi Saka
Tsuyoshi Megata
Toshihide Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP15587287A priority Critical patent/JPS64805A/en
Publication of JPH01805A publication Critical patent/JPH01805A/en
Publication of JPS64805A publication Critical patent/JPS64805A/en
Pending legal-status Critical Current

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  • Amplifiers (AREA)

Abstract

PURPOSE: To eliminate the need of a negative power source by grounding the gate terminal of an FET through a high resistance element with respect to DC.
CONSTITUTION: A gate bias resistance 10 having a high resistance RG is connected to a gate bias circuit 6. If the fundamental wave signal to be inputted from an input terminal 4 is zero or the signal level is low, the voltage between the gate and the source which is applied to one end A of the resistance 10 is equal to zero and the drain current is equal to the saturation drain current. A forward gate current IG flowing from the gate terminal of an FET 1 to the source terminal is increased according as the input level of the fundamental wave signal is raised, and a voltage equal to RG×IG is applied between the gate and the source of the FET 1. Consequently, since the negative voltage between the gate and the source is automatically impressed to the FET 1 by the resistance 10, the negative power source is unnecessary and a device is operated by a single positive power source.
COPYRIGHT: (C)1989,JPO&Japio
JP15587287A 1987-06-23 1987-06-23 Fet multiplier Pending JPS64805A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15587287A JPS64805A (en) 1987-06-23 1987-06-23 Fet multiplier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15587287A JPS64805A (en) 1987-06-23 1987-06-23 Fet multiplier

Publications (2)

Publication Number Publication Date
JPH01805A JPH01805A (en) 1989-01-05
JPS64805A true JPS64805A (en) 1989-01-05

Family

ID=15615347

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15587287A Pending JPS64805A (en) 1987-06-23 1987-06-23 Fet multiplier

Country Status (1)

Country Link
JP (1) JPS64805A (en)

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