JPS6478588A - Picture encoder - Google Patents

Picture encoder

Info

Publication number
JPS6478588A
JPS6478588A JP62236524A JP23652487A JPS6478588A JP S6478588 A JPS6478588 A JP S6478588A JP 62236524 A JP62236524 A JP 62236524A JP 23652487 A JP23652487 A JP 23652487A JP S6478588 A JPS6478588 A JP S6478588A
Authority
JP
Japan
Prior art keywords
value
output
register
counter
block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62236524A
Other languages
Japanese (ja)
Inventor
Toshihide Akiyama
Yoriyasu Takeguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62236524A priority Critical patent/JPS6478588A/en
Publication of JPS6478588A publication Critical patent/JPS6478588A/en
Pending legal-status Critical Current

Links

Landscapes

  • Compression Or Coding Systems Of Tv Signals (AREA)

Abstract

PURPOSE:To efficiently encode a picture signal by assigning an evaluation function of a block succeeding block according to the sum of the counted value of the sample number of a current block. CONSTITUTION:The data of a register 5 is subtracted in a subtracter 6 from sampling data to store the absolute value of the value in an absolute value circuit 7. Then, a sampling block Fs is inputted to a counter to count the sampling number. When the output of the absolute value circuit 7 is larger than the output of a ROM circuit 8, a comparator 9 outputs an output to feed the value Di of the counter 4 to an adder 12 and a buffer memory 10 and feeds the code Si of the output of the subtracter 6 to the buffer memory 10. Simultaneously, a value obtained by adding an initial value to the output value of the ROM 8 is latched to the register 5, the counter 4 is reset, the adder 12 adds the contents of a register 13 to the value of the fed Di and stores in the register 13.
JP62236524A 1987-09-21 1987-09-21 Picture encoder Pending JPS6478588A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62236524A JPS6478588A (en) 1987-09-21 1987-09-21 Picture encoder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62236524A JPS6478588A (en) 1987-09-21 1987-09-21 Picture encoder

Publications (1)

Publication Number Publication Date
JPS6478588A true JPS6478588A (en) 1989-03-24

Family

ID=17001969

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62236524A Pending JPS6478588A (en) 1987-09-21 1987-09-21 Picture encoder

Country Status (1)

Country Link
JP (1) JPS6478588A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0332277A (en) * 1989-06-29 1991-02-12 Alps Electric Co Ltd Method and device for compressing digital signal group
JPH0345018A (en) * 1989-07-13 1991-02-26 Alps Electric Co Ltd Method and apparatus for compressing digital signal group

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0332277A (en) * 1989-06-29 1991-02-12 Alps Electric Co Ltd Method and device for compressing digital signal group
JPH0345018A (en) * 1989-07-13 1991-02-26 Alps Electric Co Ltd Method and apparatus for compressing digital signal group

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