JPS6478028A - A/d converting circuit - Google Patents

A/d converting circuit

Info

Publication number
JPS6478028A
JPS6478028A JP23541987A JP23541987A JPS6478028A JP S6478028 A JPS6478028 A JP S6478028A JP 23541987 A JP23541987 A JP 23541987A JP 23541987 A JP23541987 A JP 23541987A JP S6478028 A JPS6478028 A JP S6478028A
Authority
JP
Japan
Prior art keywords
order bit
converter
comparison system
plural
integration type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23541987A
Other languages
Japanese (ja)
Inventor
Kazuhisa Ishiguro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP23541987A priority Critical patent/JPS6478028A/en
Publication of JPS6478028A publication Critical patent/JPS6478028A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To realize fast digital conversion with high accuracy by deciding a high-order bit by an A/D converter of prallel comparison system, and deciding only a low-order bit by a double integration type A/D converter. CONSTITUTION:The titled circuit is constituted of the A/D converter 4 of parallel comparison system to decide the high-order bit of a quantity to be digitized by comparing plural reference voltages V0-V3 with an input analog voltage Vx, and plural double integration type A/D converters 10-13 provided with charging capacitors C1, C2... Firstly, the high-order bit of the quantity to be digitized is decided by the A/D converter 4 of parallel comparison system, and one of the plural double integration type A/D converters 10-13 is selected based on the result of the high-order bit, and by inputting the reference voltage with a specific value, a capacitor C for integration is charged in advance. And next, the integration of the input analog voltage Vx is performed for a constant time. In such a way, it is possible to shorten a time to integrate an input voltage, and to reduce an A/D conversion time.
JP23541987A 1987-09-18 1987-09-18 A/d converting circuit Pending JPS6478028A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23541987A JPS6478028A (en) 1987-09-18 1987-09-18 A/d converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23541987A JPS6478028A (en) 1987-09-18 1987-09-18 A/d converting circuit

Publications (1)

Publication Number Publication Date
JPS6478028A true JPS6478028A (en) 1989-03-23

Family

ID=16985822

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23541987A Pending JPS6478028A (en) 1987-09-18 1987-09-18 A/d converting circuit

Country Status (1)

Country Link
JP (1) JPS6478028A (en)

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