JPS6477330A - Digital sample rate converting circuit - Google Patents

Digital sample rate converting circuit

Info

Publication number
JPS6477330A
JPS6477330A JP62234162A JP23416287A JPS6477330A JP S6477330 A JPS6477330 A JP S6477330A JP 62234162 A JP62234162 A JP 62234162A JP 23416287 A JP23416287 A JP 23416287A JP S6477330 A JPS6477330 A JP S6477330A
Authority
JP
Japan
Prior art keywords
sampling clock
sample rate
converting circuit
digital sample
rate converting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62234162A
Other languages
Japanese (ja)
Inventor
Tomomasa Ootsuki
Masahiro Yamada
Noriya Sakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba AVE Co Ltd
Original Assignee
Toshiba Corp
Toshiba Audio Video Engineering Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Audio Video Engineering Co Ltd filed Critical Toshiba Corp
Priority to JP62234162A priority Critical patent/JPS6477330A/en
Publication of JPS6477330A publication Critical patent/JPS6477330A/en
Pending legal-status Critical Current

Links

Landscapes

  • Color Television Systems (AREA)
  • Television Systems (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)

Abstract

PURPOSE:To remove adhere influence due to the incompleteness of stuffing dividing the period of a 1st sampling clock into plural parts and extracting the divided parts by a 2nd sampling clock. CONSTITUTION:The inverted clock 256 of the 1st sampling clock ck1 251 in a latch circuit 203 delays a signal by a half of the 1st sampling clock ck1 and the 1st sampling clock ck1 251 in a latch circuit 205 delays the input signal by a half of the 1st sampling clock ck1. The outputs of latch circuits 207, 209 are inputted to a selecting circuit 213 and outputs of latch circuits 208, 210, 212 are inputted to a selecting circuit 214. Thus, adverse influence due to the incompleteness of stuffing can be removed.
JP62234162A 1987-09-18 1987-09-18 Digital sample rate converting circuit Pending JPS6477330A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62234162A JPS6477330A (en) 1987-09-18 1987-09-18 Digital sample rate converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62234162A JPS6477330A (en) 1987-09-18 1987-09-18 Digital sample rate converting circuit

Publications (1)

Publication Number Publication Date
JPS6477330A true JPS6477330A (en) 1989-03-23

Family

ID=16966631

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62234162A Pending JPS6477330A (en) 1987-09-18 1987-09-18 Digital sample rate converting circuit

Country Status (1)

Country Link
JP (1) JPS6477330A (en)

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