JPS6477328A - Digital sample rate converter - Google Patents

Abstract

PURPOSE:To execute digital sample rate converting processing capable of reducing waveform distortion by dividing the period of the 1st sampling clock into plural parts and extracting the divided period at the 2nd sample clock. CONSTITUTION:Outputs of respective delay circuits 1701-1740 divide one period of the 1st sample clock about into 35 parts and supply the divided parts to a latch circuit 18. The circuit 18 latches the outputs of respective delay elements 1701-1740 on the basis of the sampling timing of the 2nd sampling clock supplied to an input terminal 19. The output data of the latch circuit 18 are supplied to four read-only memories(ROMs) 20-23 every 10 bits as their address data. Positional data outputted from the ROMs 20-23 are supplied to a hexadecimal output part 24 to form a hexadecimal positional data indicating the position of a down edge part out of all the data of 40 bits latched by the latch circuit 18.