JPS6477198A - Multilayer printed board - Google Patents

Multilayer printed board

Info

Publication number
JPS6477198A
JPS6477198A JP23381887A JP23381887A JPS6477198A JP S6477198 A JPS6477198 A JP S6477198A JP 23381887 A JP23381887 A JP 23381887A JP 23381887 A JP23381887 A JP 23381887A JP S6477198 A JPS6477198 A JP S6477198A
Authority
JP
Japan
Prior art keywords
layers
signal
hole
printed board
gnd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23381887A
Other languages
Japanese (ja)
Inventor
Kenichi Omae
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP23381887A priority Critical patent/JPS6477198A/en
Publication of JPS6477198A publication Critical patent/JPS6477198A/en
Pending legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To connect components packaged on both sides of a primary printed board which is constituted of GND layers and a signal layers or by only signal layers without reducing a packaging density, by laminating a secondary printed board which is constituted by only power/GND layers onto both surfaces of the primary printed board and by providing signal holes and power source holes which do not pass through all the layers. CONSTITUTION:A secondary printed boards 2 and 3 whose inner layers are constituted of only GND layers 6, 10 and power layers 7, 9 are laminated on both sides of a primary printed board 1 which has a signal wiring layers 16, 17 and a GND layer 8 through an insulation layers 4 and 5. A hole 19 in the primary printed board 1 connects a signal wiring layer 16 and a signal wiring 17 each other. A power supply hole 14 and a grounding hole 15 for packaging components on a surface are made at the position of the signal hole 19. In the rear of a signal hole 12 is a power source hole 15 thus providing a signal through-hole securely without reducing component packaging density.
JP23381887A 1987-09-18 1987-09-18 Multilayer printed board Pending JPS6477198A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23381887A JPS6477198A (en) 1987-09-18 1987-09-18 Multilayer printed board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23381887A JPS6477198A (en) 1987-09-18 1987-09-18 Multilayer printed board

Publications (1)

Publication Number Publication Date
JPS6477198A true JPS6477198A (en) 1989-03-23

Family

ID=16961051

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23381887A Pending JPS6477198A (en) 1987-09-18 1987-09-18 Multilayer printed board

Country Status (1)

Country Link
JP (1) JPS6477198A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06310870A (en) * 1993-04-21 1994-11-04 Nec Corp Wiring board structure and its manufacture

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06310870A (en) * 1993-04-21 1994-11-04 Nec Corp Wiring board structure and its manufacture

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