JPS647712A - Delaying pulse output device - Google Patents

Delaying pulse output device

Info

Publication number
JPS647712A
JPS647712A JP16129987A JP16129987A JPS647712A JP S647712 A JPS647712 A JP S647712A JP 16129987 A JP16129987 A JP 16129987A JP 16129987 A JP16129987 A JP 16129987A JP S647712 A JPS647712 A JP S647712A
Authority
JP
Japan
Prior art keywords
pulse
circuit
delaying
input
eliminated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16129987A
Other languages
Japanese (ja)
Inventor
Toshiyuki Kawamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Information Systems Ltd
Original Assignee
Hitachi Information Systems Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Information Systems Ltd filed Critical Hitachi Information Systems Ltd
Priority to JP16129987A priority Critical patent/JPS647712A/en
Publication of JPS647712A publication Critical patent/JPS647712A/en
Pending legal-status Critical Current

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  • Pulse Circuits (AREA)

Abstract

PURPOSE:To attain the pulse generation of a constant pulse even when there is no input by providing a switching circuit and switching and outputting a self-oscillation pulse when a delaying pulse is eliminated for a time longer than the frequency. CONSTITUTION:From a saw-tooth wave generating circuit 1 of a delaying pulse output part 7, a saw tooth wave is outputted in accordance with an input, compared with the controlled voltage setting freely a delaying time with a variable resistance R1 by a comparator circuit 2, a trigger output occurs from the circuit 2 at the cross point, a monostable multivibrator 4 is triggered and a delaying pulse is outputted through a switching circuit 5. The circuit 5, when the input is not executed and the delaying pulse is eliminated for a time longer than a cycle, switches and output pulse from a self-oscillation circuit 3, is input by changing over and even when the input is eliminated, the pulse of a constant cycle can be generated and the output turning off can be prevented.
JP16129987A 1987-06-30 1987-06-30 Delaying pulse output device Pending JPS647712A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16129987A JPS647712A (en) 1987-06-30 1987-06-30 Delaying pulse output device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16129987A JPS647712A (en) 1987-06-30 1987-06-30 Delaying pulse output device

Publications (1)

Publication Number Publication Date
JPS647712A true JPS647712A (en) 1989-01-11

Family

ID=15732472

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16129987A Pending JPS647712A (en) 1987-06-30 1987-06-30 Delaying pulse output device

Country Status (1)

Country Link
JP (1) JPS647712A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6305970B1 (en) 1999-11-29 2001-10-23 Yazaki Corporation Terminal end structure of flat circuitry and branch connection structure constituted by the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6305970B1 (en) 1999-11-29 2001-10-23 Yazaki Corporation Terminal end structure of flat circuitry and branch connection structure constituted by the same

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