JPS6476265A - Synchronization control system in multiprocessor system - Google Patents

Synchronization control system in multiprocessor system

Info

Publication number
JPS6476265A
JPS6476265A JP62233771A JP23377187A JPS6476265A JP S6476265 A JPS6476265 A JP S6476265A JP 62233771 A JP62233771 A JP 62233771A JP 23377187 A JP23377187 A JP 23377187A JP S6476265 A JPS6476265 A JP S6476265A
Authority
JP
Japan
Prior art keywords
plural
signal
processors
synchronizing signal
generating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62233771A
Other languages
Japanese (ja)
Inventor
Koichi Inoue
Mitsuo Ishii
Hiroaki Ishihata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62233771A priority Critical patent/JPS6476265A/en
Publication of JPS6476265A publication Critical patent/JPS6476265A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To attain plural synchronizations without increasing interface lines connecting between respective processors by time dividing a synchronizing signal transfer means to the respective processors and using. CONSTITUTION:The plural processors 31-3n are provided with a set signal generating means 4 for generating plural set signals indicating a synchronization waiting state, a multiplex means 7 for selecting one signal thereof and outputting the plural synchronization waiting states and a timing forming means 6 for generating a select signal for instructing the position of the set signal synchronously with a common start signal to the plural processors 31-3n to receive a synchronization waiting signal generated respectively by a synchronizing signal generating means 8 and transmit to the plural processors in time division through the synchronizing signal transfer means 9. Thereby, the plural synchronizations can be taken without increasing the number of synchronizing signal lines mutually connecting the processors.
JP62233771A 1987-09-18 1987-09-18 Synchronization control system in multiprocessor system Pending JPS6476265A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62233771A JPS6476265A (en) 1987-09-18 1987-09-18 Synchronization control system in multiprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62233771A JPS6476265A (en) 1987-09-18 1987-09-18 Synchronization control system in multiprocessor system

Publications (1)

Publication Number Publication Date
JPS6476265A true JPS6476265A (en) 1989-03-22

Family

ID=16960317

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62233771A Pending JPS6476265A (en) 1987-09-18 1987-09-18 Synchronization control system in multiprocessor system

Country Status (1)

Country Link
JP (1) JPS6476265A (en)

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