JPS6476238A - Data memory circuit - Google Patents

Data memory circuit

Info

Publication number
JPS6476238A
JPS6476238A JP23251787A JP23251787A JPS6476238A JP S6476238 A JPS6476238 A JP S6476238A JP 23251787 A JP23251787 A JP 23251787A JP 23251787 A JP23251787 A JP 23251787A JP S6476238 A JPS6476238 A JP S6476238A
Authority
JP
Japan
Prior art keywords
memory
cpu
data
microcomputer
contents
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23251787A
Other languages
Japanese (ja)
Inventor
Toshimasa Tanaka
Nobuo Matsui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP23251787A priority Critical patent/JPS6476238A/en
Publication of JPS6476238A publication Critical patent/JPS6476238A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To observe the internal operation of a microcomputer from a external part by providing first and second memories where one and the same address is allocated, separing the second and a CPU and thereafter, outputting the storing contents of the second memory. CONSTITUTION:In a data memory circuit 4 of a CPU part 2 to constitute the microcomputer, the same address is allocated to a first memory 16 and a second memory 19. When the CPU part 2 executes the writing operation of data to the first memory 16, simultaneously with this operation, the same data are written to the second memory 19. When a prescribed instruction is given, the second memory 19 is separated from the CPU part 2 by a data output control part. Simultaneously, the contents to be stored to the second memory 19 is outputted to the external part regardless of the operation of the CPU part 2. Thus, without giving a burden to the CPU part 2, the contents operation of the microcomputer can be easily observed from the external part successively at real time.
JP23251787A 1987-09-18 1987-09-18 Data memory circuit Pending JPS6476238A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23251787A JPS6476238A (en) 1987-09-18 1987-09-18 Data memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23251787A JPS6476238A (en) 1987-09-18 1987-09-18 Data memory circuit

Publications (1)

Publication Number Publication Date
JPS6476238A true JPS6476238A (en) 1989-03-22

Family

ID=16940569

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23251787A Pending JPS6476238A (en) 1987-09-18 1987-09-18 Data memory circuit

Country Status (1)

Country Link
JP (1) JPS6476238A (en)

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