JPS6476165A - Data interpolation device - Google Patents

Data interpolation device

Info

Publication number
JPS6476165A
JPS6476165A JP23280987A JP23280987A JPS6476165A JP S6476165 A JPS6476165 A JP S6476165A JP 23280987 A JP23280987 A JP 23280987A JP 23280987 A JP23280987 A JP 23280987A JP S6476165 A JPS6476165 A JP S6476165A
Authority
JP
Japan
Prior art keywords
data
delay
signals
outputted
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23280987A
Other languages
Japanese (ja)
Inventor
Hajime Koyama
Rei Kurokawa
Hiromoto Fujioka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP23280987A priority Critical patent/JPS6476165A/en
Publication of JPS6476165A publication Critical patent/JPS6476165A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To generate optimum interpolating data by providing a delay data selecting circuit for selecting plural signals from plural delay data signals and data signals different in the quantity of delay according to the change speed of the data signal and applying an operation between the selected signals. CONSTITUTION:The data signal 100 and a clock signal 103 are inputted to the data delay circuit 1 and the plural delay data signals 101, 102 having the different quantity of delay are outputted. In the delay data selecting circuit 2, two of the plural delay data signals 101, 102 and the data signal 100 are selected and outputted by a selecting signal 104 and outputted. Signals 105, 106 outputted from the delay data selecting circuit 2 are added in an addition circuit 3. Then, a dividing circuit 4 divides a signal outputted from the addition circuit 3.
JP23280987A 1987-09-17 1987-09-17 Data interpolation device Pending JPS6476165A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23280987A JPS6476165A (en) 1987-09-17 1987-09-17 Data interpolation device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23280987A JPS6476165A (en) 1987-09-17 1987-09-17 Data interpolation device

Publications (1)

Publication Number Publication Date
JPS6476165A true JPS6476165A (en) 1989-03-22

Family

ID=16945105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23280987A Pending JPS6476165A (en) 1987-09-17 1987-09-17 Data interpolation device

Country Status (1)

Country Link
JP (1) JPS6476165A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100819972B1 (en) * 2003-09-30 2008-04-08 가부시끼가이샤 도시바 Rotor of motor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100819972B1 (en) * 2003-09-30 2008-04-08 가부시끼가이샤 도시바 Rotor of motor

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