JPS6474655A - Communication system - Google Patents

Communication system

Info

Publication number
JPS6474655A
JPS6474655A JP23176087A JP23176087A JPS6474655A JP S6474655 A JPS6474655 A JP S6474655A JP 23176087 A JP23176087 A JP 23176087A JP 23176087 A JP23176087 A JP 23176087A JP S6474655 A JPS6474655 A JP S6474655A
Authority
JP
Japan
Prior art keywords
signal
circuit
cpu
designated
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23176087A
Other languages
Japanese (ja)
Inventor
Katsuzumi Inasawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP23176087A priority Critical patent/JPS6474655A/en
Publication of JPS6474655A publication Critical patent/JPS6474655A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol

Abstract

PURPOSE:To simplify communication protocol to reduce time restriction for control by connecting a first circuit and second - n-th circuits by four-wire bus lines and transmitting signal indicating the timing at the time of possibility of data transmission and reception. CONSTITUTION:When a CPU 1 sets a signal R and A to a low level and reports the start of transfer to an IC circuit, its own signal R and A is set to the low level to set the output mode. After a prescribed time, the CPU 1 sends signals A and C synchronously with the clock of a line 34. The signal C is received by a circuit designated by the signal A to set a terminal Rx to the inputtable state. The CPU 1 and the designated circuit return signals R and A to a high level, and circuits which are not designated return signals R and A to the high level after receiving the signal A. The CPU 1 supplies data D to the terminal Rx of the designated circuit together with the clock after sending the signal C. Thus, the communication protocol is simplified to reduce the time restriction for control.
JP23176087A 1987-09-16 1987-09-16 Communication system Pending JPS6474655A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23176087A JPS6474655A (en) 1987-09-16 1987-09-16 Communication system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23176087A JPS6474655A (en) 1987-09-16 1987-09-16 Communication system

Publications (1)

Publication Number Publication Date
JPS6474655A true JPS6474655A (en) 1989-03-20

Family

ID=16928599

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23176087A Pending JPS6474655A (en) 1987-09-16 1987-09-16 Communication system

Country Status (1)

Country Link
JP (1) JPS6474655A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102861832A (en) * 2012-09-28 2013-01-09 天津博信汽车零部件有限公司 Automatic basketing system for workpieces

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102861832A (en) * 2012-09-28 2013-01-09 天津博信汽车零部件有限公司 Automatic basketing system for workpieces

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