JPS6474654A - Data transfer controller - Google Patents

Data transfer controller

Info

Publication number
JPS6474654A
JPS6474654A JP23313287A JP23313287A JPS6474654A JP S6474654 A JPS6474654 A JP S6474654A JP 23313287 A JP23313287 A JP 23313287A JP 23313287 A JP23313287 A JP 23313287A JP S6474654 A JPS6474654 A JP S6474654A
Authority
JP
Japan
Prior art keywords
address
data
circuit
memory
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23313287A
Other languages
Japanese (ja)
Inventor
Yukio Uchiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP23313287A priority Critical patent/JPS6474654A/en
Publication of JPS6474654A publication Critical patent/JPS6474654A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To reduce the amount of hardware to simplify the control by dividing data from a storage device to partial data and distributing these partial data to desired storage parts in 1:1 to store them in designated storage positions. CONSTITUTION:An address circuit 7 sends address information indicating an address (n) to an address operating circuit 8 and a local memory part 6. The circuit 8 sends this information to a local memory part 5 as it is. Next, word data in an address N of a system memory 1 is transferred to a data handling circuit 4 by the control of a direct memory access DMA control circuit. The circuit 4 stores high-order byte data and low-order byte data of data in the address (n) of memory parts 5 and 6. Hereafter, word data in an address N+1 and following addresses of the memory 1 are stored in an address n+1 and following address of a memory 12 similarly. Thus, the amount of hardware is reduced to simplify the control.
JP23313287A 1987-09-16 1987-09-16 Data transfer controller Pending JPS6474654A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23313287A JPS6474654A (en) 1987-09-16 1987-09-16 Data transfer controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23313287A JPS6474654A (en) 1987-09-16 1987-09-16 Data transfer controller

Publications (1)

Publication Number Publication Date
JPS6474654A true JPS6474654A (en) 1989-03-20

Family

ID=16950241

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23313287A Pending JPS6474654A (en) 1987-09-16 1987-09-16 Data transfer controller

Country Status (1)

Country Link
JP (1) JPS6474654A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6285326A (en) * 1985-10-09 1987-04-18 Nec Corp Register file system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6285326A (en) * 1985-10-09 1987-04-18 Nec Corp Register file system

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