JPS6474630A - Interrupt circuit - Google Patents

Interrupt circuit

Info

Publication number
JPS6474630A
JPS6474630A JP23192387A JP23192387A JPS6474630A JP S6474630 A JPS6474630 A JP S6474630A JP 23192387 A JP23192387 A JP 23192387A JP 23192387 A JP23192387 A JP 23192387A JP S6474630 A JPS6474630 A JP S6474630A
Authority
JP
Japan
Prior art keywords
cpu
output
address
allowing
outputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23192387A
Other languages
Japanese (ja)
Inventor
Yoshiaki Haniyu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP23192387A priority Critical patent/JPS6474630A/en
Publication of JPS6474630A publication Critical patent/JPS6474630A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To use a CPU allowing a single interrupt as the CPU allowing plural interrupts by performing switching between the output of a priority encoder and an arbitrary address outputted from the CPU in accordance with the output of a vector address decoder. CONSTITUTION:An interrupt request signal generating circuit 16 outputs an interrupt request signal to a CPU 11. A priority encoder 17 gives priority levels to plural interrupts signals and encodes them, and a vector address decoder 18 decodes the vector address which the CPU 11 outputs. A multiplexer 19 performs switching between the output of the encoder 17 and an arbitrary address outputted from the CPU 11 in accordance with the output of the decoder 18, and the switched output of the multiplexer 19 is supplied to a ROM 15 including a vector address area. Then, the address value as the input of the ROM 15 is changed, and contents of this address are outputted to a data bus 14. Thus, the CPU allowing a single interrupt is used as the CPU allowing plural interrupts.
JP23192387A 1987-09-16 1987-09-16 Interrupt circuit Pending JPS6474630A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23192387A JPS6474630A (en) 1987-09-16 1987-09-16 Interrupt circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23192387A JPS6474630A (en) 1987-09-16 1987-09-16 Interrupt circuit

Publications (1)

Publication Number Publication Date
JPS6474630A true JPS6474630A (en) 1989-03-20

Family

ID=16931179

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23192387A Pending JPS6474630A (en) 1987-09-16 1987-09-16 Interrupt circuit

Country Status (1)

Country Link
JP (1) JPS6474630A (en)

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