JPS6473655A - Multilayer interconnection board - Google Patents

Multilayer interconnection board

Info

Publication number
JPS6473655A
JPS6473655A JP62231602A JP23160287A JPS6473655A JP S6473655 A JPS6473655 A JP S6473655A JP 62231602 A JP62231602 A JP 62231602A JP 23160287 A JP23160287 A JP 23160287A JP S6473655 A JPS6473655 A JP S6473655A
Authority
JP
Japan
Prior art keywords
semiconductor integrated
integrated circuit
circuit chip
cavities
metal sheet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62231602A
Other languages
Japanese (ja)
Inventor
Yoshimi Marui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62231602A priority Critical patent/JPS6473655A/en
Publication of JPS6473655A publication Critical patent/JPS6473655A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE:To enhance mounting efficiency and to enhance heat-dissipating performance by a method wherein a metal pattern connected to an electrode of a semiconductor integrated circuit chip by using a bonding wire and a metal sheet used to mount and bond the semiconductor integrated circuit chip to the bottom of a cavity are provided on the main surface in the circumference of the cavity. CONSTITUTION:In a multilayer interconnection board 12, 12 rows of cavities 3 to house each semiconductor integrated circuit chip directly end a metal sheet 4 for mounting use on the bottom of the cavities 3 are provided. The semiconductor integrated circuit chip 9 is bonded to the metal sheet 4 for mounting use on the bottom of the cavities 3; the semiconductor integrated circuit chip 9 is connected to a metal pattern 5 for connection terminal use on the multilayer printed-circuit board 12 by using a bonding wire 6. The semiconductor integrated circuit chip 9 is mounted on the metal sheet 4 for mounting use on the bottom of the cavities 3 by a bonding means such as a conductive epoxy adhesive or the like; after that, the semiconductor integrated circuit chip 9 is connected to the metal pattern 5 for connection terminal use on the main surface of the multilayer printed-circuit board 12 by using a wire-bonding means.
JP62231602A 1987-09-14 1987-09-14 Multilayer interconnection board Pending JPS6473655A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62231602A JPS6473655A (en) 1987-09-14 1987-09-14 Multilayer interconnection board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62231602A JPS6473655A (en) 1987-09-14 1987-09-14 Multilayer interconnection board

Publications (1)

Publication Number Publication Date
JPS6473655A true JPS6473655A (en) 1989-03-17

Family

ID=16926084

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62231602A Pending JPS6473655A (en) 1987-09-14 1987-09-14 Multilayer interconnection board

Country Status (1)

Country Link
JP (1) JPS6473655A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5314835A (en) * 1989-06-20 1994-05-24 Sharp Kabushiki Kaisha Semiconductor memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5314835A (en) * 1989-06-20 1994-05-24 Sharp Kabushiki Kaisha Semiconductor memory device
US5334869A (en) * 1989-06-20 1994-08-02 Sharp Kabushiki Kaisha Semiconductor memory device

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