JPS647201A - Sequence debugging system - Google Patents
Sequence debugging systemInfo
- Publication number
- JPS647201A JPS647201A JP62163387A JP16338787A JPS647201A JP S647201 A JPS647201 A JP S647201A JP 62163387 A JP62163387 A JP 62163387A JP 16338787 A JP16338787 A JP 16338787A JP S647201 A JPS647201 A JP S647201A
- Authority
- JP
- Japan
- Prior art keywords
- condition
- time
- clock
- input
- holding means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE:To shorten a debugging working time and to improve a working efficiency by stepping back to a certain past point of time, reproducing a condition, re-executing the input of a sequence after the point of time and replaying after the point of time in a debugging working. CONSTITUTION:An external input signal Si is sequentially stored to an input signal preserving buffer means 8 times synchronized to the period of which is settable, an input condition, an internal condition output condition and the period of on step-back clock CPS are stored into a condition preserving buffer means 10 times synchronized with the step-back clock CPS which frequency divides the master clock CP. In the replaying mode, the contents of the condition preserving buffer means 10 are set to an input condition holding means 2, an internal condition holding means 3, an output condition holding means 5 and a aster clock generating means 6 in the unit of the stepback clock CPS, the contents of the input signal preserving buffer means 8 are inputted to the input condition holding means 2 and the later sequence is reproduced. Thus, the time and manday can be shortened.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62163387A JPS647201A (en) | 1987-06-30 | 1987-06-30 | Sequence debugging system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62163387A JPS647201A (en) | 1987-06-30 | 1987-06-30 | Sequence debugging system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS647201A true JPS647201A (en) | 1989-01-11 |
Family
ID=15772922
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62163387A Pending JPS647201A (en) | 1987-06-30 | 1987-06-30 | Sequence debugging system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS647201A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5798008A (en) * | 1980-12-11 | 1982-06-18 | Mitsubishi Electric Corp | Reproducing method of operation contents in monitor controlling device |
JPS57120117A (en) * | 1981-01-17 | 1982-07-27 | Mitsubishi Electric Corp | Regenerating device |
-
1987
- 1987-06-30 JP JP62163387A patent/JPS647201A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5798008A (en) * | 1980-12-11 | 1982-06-18 | Mitsubishi Electric Corp | Reproducing method of operation contents in monitor controlling device |
JPS57120117A (en) * | 1981-01-17 | 1982-07-27 | Mitsubishi Electric Corp | Regenerating device |
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