JPS6471349A - Signal processing circuit - Google Patents

Signal processing circuit

Info

Publication number
JPS6471349A
JPS6471349A JP62229025A JP22902587A JPS6471349A JP S6471349 A JPS6471349 A JP S6471349A JP 62229025 A JP62229025 A JP 62229025A JP 22902587 A JP22902587 A JP 22902587A JP S6471349 A JPS6471349 A JP S6471349A
Authority
JP
Japan
Prior art keywords
signal
speed
processing circuit
processing
multiplex
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62229025A
Other languages
Japanese (ja)
Inventor
Nobuo Sugino
Yoshikazu Suehiro
Kazuo Matsumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62229025A priority Critical patent/JPS6471349A/en
Publication of JPS6471349A publication Critical patent/JPS6471349A/en
Pending legal-status Critical Current

Links

Landscapes

  • Communication Control (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To send a low-speed signal without losing characteristics of a high- speed signal by using other multiplex processing circuits for a signal group requiring high-speed processing and a signal group enough to be subjected to low-speed processing respectively. CONSTITUTION:A high-speed signal A-1 requiring high-speed processing in a transmission line A is supplied to a multiplex signal processing circuit 1. Moreover, a remaining low-speed signal A-2 allowing low-speed processing is fed to the multiplex signal processing circuit 2. The high-speed signal B-1 is fed to the processing circuit 1 from the other transmission signal line B and the low-speed signal B-2 is fed to the processing circuit 2. Then the processing circuit 2 uses a multiplex start signal E from the processing circuit 1 to apply time division multiplex to the low-speed signal and supplies an output signal C to the processing circuit 1. The processing circuit 1 receiving it applies the time division multiplex processing to the high-speed signal and the output signal C to send a multiplex transmission signal D to the transmission line.
JP62229025A 1987-09-11 1987-09-11 Signal processing circuit Pending JPS6471349A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62229025A JPS6471349A (en) 1987-09-11 1987-09-11 Signal processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62229025A JPS6471349A (en) 1987-09-11 1987-09-11 Signal processing circuit

Publications (1)

Publication Number Publication Date
JPS6471349A true JPS6471349A (en) 1989-03-16

Family

ID=16885569

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62229025A Pending JPS6471349A (en) 1987-09-11 1987-09-11 Signal processing circuit

Country Status (1)

Country Link
JP (1) JPS6471349A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5833334A (en) * 1981-08-21 1983-02-26 Hitachi Ltd Time division multiplexing device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5833334A (en) * 1981-08-21 1983-02-26 Hitachi Ltd Time division multiplexing device

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