JPS6470828A - Bit series integration circuit - Google Patents

Bit series integration circuit

Info

Publication number
JPS6470828A
JPS6470828A JP63207497A JP20749788A JPS6470828A JP S6470828 A JPS6470828 A JP S6470828A JP 63207497 A JP63207497 A JP 63207497A JP 20749788 A JP20749788 A JP 20749788A JP S6470828 A JPS6470828 A JP S6470828A
Authority
JP
Japan
Prior art keywords
shift register
signal
coupled
integration circuit
stage shift
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63207497A
Other languages
English (en)
Other versions
JPH0421218B2 (ja
Inventor
Jiei Kurisutofuaa Totsudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RCA Licensing Corp
Original Assignee
RCA Licensing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RCA Licensing Corp filed Critical RCA Licensing Corp
Publication of JPS6470828A publication Critical patent/JPS6470828A/ja
Publication of JPH0421218B2 publication Critical patent/JPH0421218B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50Adding; Subtracting
    • G06F7/504Adding; Subtracting in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other
    • G06F7/5045Adding; Subtracting in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other for multiple operands
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942Significance control
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49994Sign extension

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
  • Dc Digital Transmission (AREA)
  • Manipulation Of Pulses (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
JP63207497A 1987-08-24 1988-08-23 Bit series integration circuit Granted JPS6470828A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/088,340 US4841466A (en) 1987-08-24 1987-08-24 Bit-serial integrator circuitry

Publications (2)

Publication Number Publication Date
JPS6470828A true JPS6470828A (en) 1989-03-16
JPH0421218B2 JPH0421218B2 (ja) 1992-04-09

Family

ID=22210796

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63207497A Granted JPS6470828A (en) 1987-08-24 1988-08-23 Bit series integration circuit

Country Status (8)

Country Link
US (1) US4841466A (ja)
EP (1) EP0304841B1 (ja)
JP (1) JPS6470828A (ja)
KR (1) KR0128505B1 (ja)
CN (1) CN1014936B (ja)
CA (1) CA1290458C (ja)
DE (1) DE3853655T2 (ja)
FI (1) FI93284C (ja)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5313469A (en) * 1993-06-11 1994-05-17 Northern Telecom Limited Self-testable digital integrator
EP1001567A1 (en) 1998-11-13 2000-05-17 TELEFONAKTIEBOLAGET LM ERICSSON (publ) Combiner
EP1011281A3 (en) 1998-12-18 2000-07-05 TELEFONAKTIEBOLAGET L M ERICSSON (publ) Flexible CDMA combiner
US8008731B2 (en) 2005-10-12 2011-08-30 Acco IGFET device having a RF capability
TWI444021B (zh) * 2007-09-17 2014-07-01 Htc Corp 解譯串列傳輸訊號之方法
US7808415B1 (en) * 2009-03-25 2010-10-05 Acco Semiconductor, Inc. Sigma-delta modulator including truncation and applications thereof
TWI426397B (zh) * 2009-06-29 2014-02-11 Lee Ming Inst Technology Can be used in a signal interval in the unequal spacing of the sample, the signal in this interval between a single and multiple numerical integration device.
US8532584B2 (en) 2010-04-30 2013-09-10 Acco Semiconductor, Inc. RF switches

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3757261A (en) * 1972-02-11 1973-09-04 Collins Radio Co Integration and filtration circuit apparatus
US3919535A (en) * 1974-08-21 1975-11-11 Singer Co Multiple addend adder and multiplier
US4023019A (en) * 1974-09-23 1977-05-10 The United States Of America As Represented By The Secretary Of The Navy Automatic scaled digital integrator
SU739566A1 (ru) * 1978-01-04 1980-06-05 Предприятие П/Я А-3890 Цифровой интегратор
US4246642A (en) * 1979-01-22 1981-01-20 Ricoh Company, Ltd. Leaky digital integrator
JPH105347A (ja) * 1996-06-21 1998-01-13 Toyo Sangyo Kk 低周波治療器

Also Published As

Publication number Publication date
CA1290458C (en) 1991-10-08
DE3853655T2 (de) 1995-10-19
DE3853655D1 (de) 1995-06-01
EP0304841A2 (en) 1989-03-01
KR0128505B1 (ko) 1998-04-15
FI93284C (fi) 1995-03-10
US4841466A (en) 1989-06-20
CN1014936B (zh) 1991-11-27
KR890004233A (ko) 1989-04-20
EP0304841A3 (en) 1991-03-20
FI93284B (fi) 1994-11-30
FI883816A (fi) 1989-02-25
EP0304841B1 (en) 1995-04-26
CN1031768A (zh) 1989-03-15
FI883816A0 (fi) 1988-08-17
JPH0421218B2 (ja) 1992-04-09

Similar Documents

Publication Publication Date Title
AU6392686A (en) Digital intergrated circuit
CA1270534C (en) SHIFT DEVICE
JPS6470828A (en) Bit series integration circuit
JPS53116134A (en) Peak holding circuit
JPS6490618A (en) High speed continuous approximation register in analog-to-digital converter
JPS5647125A (en) Delay circuit
JPS6486271A (en) Accumulator
JPS573293A (en) Delay circuit
JPS5792484A (en) Timing pulse generating circuit
JPS6472230A (en) Bit inverter
JPS5612153A (en) Majority-deciding circuit
SU841049A1 (ru) Ячейка пам ти дл регистра сдвига
SU788375A1 (ru) Преобразователь интервала времени в цифровой код
JPS6458111A (en) Digital mixer
JPS55115722A (en) Control unit
JPS5637890A (en) Static sequence circuit
JPS57196688A (en) Multiplexing system for dial pulse transmission trunk
JPS5578616A (en) Digital signal attenuator
JPS6436331A (en) Arithmetic processing circuit
JPS6442733A (en) Adder using 2m-a as modulus
JPS5684028A (en) Pulse generating circuit
JPS54131842A (en) Selection device for maximum value holding register
JPS648558A (en) Signal processing circuit
JPS5353934A (en) Integration circuit for constituting shift register
JPS5750137A (en) Counter

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees