JPS6469056A - Manufacture of mos semiconductor device - Google Patents
Manufacture of mos semiconductor deviceInfo
- Publication number
- JPS6469056A JPS6469056A JP22736887A JP22736887A JPS6469056A JP S6469056 A JPS6469056 A JP S6469056A JP 22736887 A JP22736887 A JP 22736887A JP 22736887 A JP22736887 A JP 22736887A JP S6469056 A JPS6469056 A JP S6469056A
- Authority
- JP
- Japan
- Prior art keywords
- film
- chemical vapor
- insulating film
- oxide film
- drain regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE:To inhibit ions while stabilizing the operation of an integrated circuit by applying a silicon oxide film through a high-temperature CVD method onto a conductor film as an ion implanting mask material for forming source-drain regions. CONSTITUTION:A gate oxide film 2 is shaped onto the surface of a silicon substrate 1, a high-melting-point metal is applied by using a puttering method or a chemical vapor growth method, and a conductor film 3 is formed. An insulating film 4 is formed using a low-pressure chemical vapor deposition (CVD) device, in which the inside of a reaction tube is held at 700-1000 deg.C, and a silicon oxide film is deposited through the chemical vapor phase reaction of dichlorosilane (SiH2Cl2) and nitrous oxide gas (N2O) under low pressure. 1000-1500Angstrom are preferable as film thickness because the insulating film 4 is used as a mask material for ion implantation. The insulating film 4 and the conductor film 3 are formed into desired shaped through a standard photoetching method and a reactive ion etching method. N-type or P-type im purity ions 6 are implanted for shaping source-drain regions 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22736887A JPS6469056A (en) | 1987-09-10 | 1987-09-10 | Manufacture of mos semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22736887A JPS6469056A (en) | 1987-09-10 | 1987-09-10 | Manufacture of mos semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6469056A true JPS6469056A (en) | 1989-03-15 |
Family
ID=16859708
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22736887A Pending JPS6469056A (en) | 1987-09-10 | 1987-09-10 | Manufacture of mos semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6469056A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6884295B2 (en) | 2000-05-29 | 2005-04-26 | Tokyo Electron Limited | Method of forming oxynitride film or the like and system for carrying out the same |
-
1987
- 1987-09-10 JP JP22736887A patent/JPS6469056A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6884295B2 (en) | 2000-05-29 | 2005-04-26 | Tokyo Electron Limited | Method of forming oxynitride film or the like and system for carrying out the same |
| US7211295B2 (en) | 2000-05-29 | 2007-05-01 | Tokyo Electron Limited | Silicon dioxide film forming method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4925805A (en) | Method of manufacturing a semiconductor device having an SOI structure using selectable etching | |
| EP0138978B1 (en) | Method of manufacturing a semiconductor device having small dimensions | |
| US7776761B2 (en) | Method of fabricating semiconductor device having multiple gate insulating layer | |
| JPH0456471B2 (en) | ||
| US7326631B2 (en) | Method of manufacturing MOS transistors with gate electrodes formed in a packet of metal layers deposited upon one another | |
| JPH01147829A (en) | Manufacture of semiconductor device | |
| US4948744A (en) | Process of fabricating a MISFET | |
| US6004872A (en) | Method of manufacturing semiconductor device | |
| JPS6469056A (en) | Manufacture of mos semiconductor device | |
| US3936321A (en) | Method of making a compound semiconductor layer of high resistivity | |
| US20110306171A1 (en) | Methods of fabricating semiconductor devices with differentially nitrided gate insulators | |
| KR100564416B1 (en) | Salicide layer formation method of semiconductor device | |
| US20020081811A1 (en) | Low-temperature deposition of silicon nitride/oxide stack | |
| CN111739943B (en) | Field effect power transistor and manufacturing method thereof | |
| GB2300517A (en) | Method of manufacturing a semiconductor device | |
| JPS56107552A (en) | Manufacture of semiconductor device | |
| JPS63300563A (en) | Manufacture of mos field-effect transistor | |
| JPS6455865A (en) | Manufacture of semiconductor device | |
| KR920010123B1 (en) | Metal wired-film forming method | |
| WO1986001641A1 (en) | Mos transistors having schottky layer electrode regions and method of their production | |
| JPS57106169A (en) | Manufacture of semiconductor device | |
| TW306018B (en) | The RTCVD method of dual gates CMOS | |
| KR100256246B1 (en) | Method of forming gate electrode in semiconductor device | |
| JPS63261879A (en) | Manufacture of semiconductor device | |
| JPS61207076A (en) | Manufacture of semiconductor device |