CN111739943B - Field effect power transistor and manufacturing method thereof - Google Patents

Field effect power transistor and manufacturing method thereof Download PDF

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Publication number
CN111739943B
CN111739943B CN202010656192.7A CN202010656192A CN111739943B CN 111739943 B CN111739943 B CN 111739943B CN 202010656192 A CN202010656192 A CN 202010656192A CN 111739943 B CN111739943 B CN 111739943B
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region
substrate
layer
manufacturing
oxide layer
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CN111739943A (en
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宋滨
陈越
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Jilin Sino Microelectronics Co Ltd
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Jilin Sino Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

The embodiment of the application provides a field effect power transistor and a manufacturing method thereof, and relates to the technical field of semiconductor device manufacturing. Through controlling the thickness of the gate oxide layer and the polycrystalline layer, the injected positive valence ions (such as boron positive ions) are effectively prevented from entering the JFET region in the manufacturing process of the P-type body region, negative valence ions (such as phosphorus negative ions) in the JFET region are neutralized, the concentration of conductive ions in the JFET region is reduced, the stability of the concentration of conductive ions in the JFET region is ensured, double-power etching is used for controlling the over etching quantity of an N+ region doped ion region in lead hole etching, the fact that the concentration of the N+ region doped ions cannot be obviously reduced due to over etching is ensured, the repeatability and the stability of the concentration of the N+ region doped ions are ensured, and accordingly, the relatively stable RDSON parameters of different field effect transistors in batches or in the same batch are ensured.

Description

Field effect power transistor and manufacturing method thereof
Technical Field
The application relates to the technical field of semiconductor device manufacturing, in particular to a field effect power transistor and a manufacturing method thereof.
Background
The field effect power transistor is widely used in electronic products in various fields of national economy, for example, a Vertical Double diffusion metal oxide semiconductor field effect transistor (VDMOS) in the field effect transistor has important significance on product performance, and how to ensure that different field effect transistors in a batch or the same batch maintain relatively stable RDSON parameters during the production process of the field effect power transistor is a technical problem which needs to be solved urgently for a person skilled in the art.
Disclosure of Invention
In order to overcome the technical problems mentioned in the background art, embodiments of the present application provide a field effect power transistor and a method for manufacturing the same.
In a first aspect of the present application, a method for manufacturing a field effect power transistor is provided, the method comprising:
providing a substrate (101);
manufacturing a JFET region (104) and P-well regions (103) positioned on two sides of the JFET region (104) on the upper surface of the substrate (101);
manufacturing a gate oxide layer (105) with the thickness ranging from 400 to 1200 angstroms on one side of the upper surface of the substrate (101);
manufacturing a polycrystalline layer (106) with the thickness not less than 5500 angstroms on the side, far away from the substrate (101), of the gate oxide layer (105);
etching the polycrystalline layer (106) and the gate oxide layer (105) to form a P-type body region window, and manufacturing a P-type body region (107) on the upper surface of the substrate (101) through ion implantation and junction pushing treatment;
-forming an n+ region (108) on the P-type body region (107), the n+ region (108) being adjacent to the P-well region (103);
depositing an insulating layer (109) on the upper surface side of the substrate (101);
etching the insulating layer (109) on opposite sides of the upper surface of the substrate (101);
manufacturing a first metal layer (110) on one side of the upper surface of the substrate (101), wherein the first metal layer (110) is in contact with the P well region (103) and the N+ region (108);
a second metal layer (111) is formed on the lower surface side of the substrate (101).
In one possible embodiment of the present application, fabricating a JFET region (104) and a P-well region (103) on an upper surface of the substrate (101) includes:
growing an oxide layer (102) with a thickness ranging from 4000 angstroms to 5000 angstroms on the upper surface of the substrate (101);
etching to form JFET region windows and P-well region windows on the oxide layer (102) respectively;
implanting ions into the substrate (101) through the JFET region window and the P-well region window, respectively;
and performing junction pushing treatment on the substrate (101) after ion implantation, and forming a JFET region (104) and a P-well region (103) on the upper surface of the substrate (101).
In one possible embodiment of the present application, the gate oxide layer (105) having a thickness in a range of 400-1200 angstroms is formed on the upper surface side of the substrate (101), and includes:
and growing a gate oxide layer (105) with the thickness ranging from 400 to 1200 angstroms on one side of the upper surface of the substrate (101) in a growth temperature range of 950-1100 ℃ under a growth environment of pure oxygen and trichloroethylene.
In one possible embodiment of the present application, fabricating a polysilicon layer (106) having a thickness of not less than 5500 angstroms on a side of the gate oxide layer (105) remote from the substrate (101), comprising:
and growing a polycrystalline layer (106) with a thickness of not less than 5500 angstroms on the side of the gate oxide layer (105) away from the substrate (101) at a growth temperature ranging from 500-800 ℃.
In one possible embodiment of the present application, fabricating an n+ region (108) on the P-type body region (107) includes:
coating a photoresist layer on the P-type body region (107);
etching the photoresist layer to obtain an N+ region window;
and implanting arsenic ions with the dosage not less than 3E15 into the P-type body region (107) through the N+ region window at the implantation energy of 100-130Kev to obtain an N+ region (108).
In one possible embodiment of the present application, etching the insulating layer (109) located on opposite sides of the upper surface of the substrate (101) includes:
coating a photoresist layer on the insulating layer (109);
etching the photoresist layer, and etching lead area windows on the insulating layers (109) on two opposite sides of the upper surface of the substrate (101);
and etching the insulating layer (109) corresponding to the lead area window by adopting a mode of firstly high etching power and then low etching power, and exposing the N+ area (108).
In one possible embodiment of the present application, the manufacturing method further includes:
removing the photoresist in the lead area window by adopting a twice dry method;
removing an oxide layer and residual glue on the upper surface of the substrate (101) by adopting a mixed solution comprising an HF solution, an SC-1 solution and an SC-2 solution, wherein the SC-1 solution comprises NH with a mass ratio of 1:1:5-1:5:10 4 OH、H 2 O 2 H and H 2 The O, SC-2 solution comprises HCL and H with the mass ratio of 1:1:5-1:5:10 2 O 2 H and H 2 O。
In one possible embodiment of the present application, after fabricating the first metal layer (110) based on the upper surface side of the substrate (101), the fabricating method further includes:
and alloying the first metal layer (110) and the substrate (101) in a working environment with a temperature of 400 ℃ and a gaseous environment of a mixed gas of nitrogen and hydrogen.
In a second aspect of the present application, there is also provided a field effect power transistor, comprising:
a substrate (101);
the JFET region (104) is manufactured on the upper surface of the substrate (101), and the P-well regions (103) are positioned on two sides of the JFET region (104);
a P-type body region (107) formed on the upper surface of the substrate (101) and located between the P-well region (103) and the JFET region (104), wherein the P-well region (103) is doped with positive ions, and the P-type body region (107) is also doped with positive ions;
an N+ region (108) formed on the P-type body region (107) and adjacent to the P-well region (103);
the grid oxide layer (105) is manufactured on one side of the upper surface of the substrate (101), the grid oxide layer (105) at least covers the JFET region (104), and the thickness of the grid oxide layer (105) is 400-1200 angstroms;
a polycrystalline layer (106) which is manufactured on one side of the gate oxide layer (105) far away from the substrate (101), wherein the thickness of the polycrystalline layer (106) is not less than 5500 angstroms;
an insulating layer (109) formed on one side of the upper surface of the substrate (101), wherein the insulating layer (109) covers the polycrystalline layer (106);
the first metal layer (110) is manufactured on one side of the upper surface of the substrate (101), the first metal layer (110) covers the insulating layer (109), and the first metal layer (110) is in contact with the P well region (103) and the N+ region (108);
and a second metal layer (111) formed on the lower surface side of the substrate (101).
In one possible embodiment of the present application, the insulating layer (109) has a thickness of 8000-10000 angstroms.
According to the field effect power transistor and the manufacturing method thereof, the thickness of the gate oxide layer (105) and the thickness of the polycrystalline layer (106) are controlled, positive ions (such as boron positive ions) injected into the JFET region (104) are effectively prevented from entering the manufacturing process of the P-type body region (107), negative ions (such as phosphorus negative ions) in the JFET region (104) are neutralized, the concentration of conductive ions in the JFET region (104) is reduced, the concentration of the conductive ions in the JFET region (104) is ensured to be stable, and accordingly relatively stable RDSON parameters of different field effect transistors in batches or in the same batch are ensured to be maintained.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered limiting the scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural cross-sectional view of a field effect power transistor according to an embodiment of the present disclosure;
fig. 2 is a schematic flow chart of a method for fabricating the field effect power transistor in fig. 1 according to an embodiment of the present application;
fig. 3A-3K are process diagrams for fabricating the fet of fig. 1 according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present application, it should be noted that, the azimuth or positional relationship indicated by the terms "upper", "lower", etc. are based on the azimuth or positional relationship shown in the drawings, or the azimuth or positional relationship that is commonly put when the product of the application is used, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element to be referred to must have a specific azimuth, be configured and operated in a specific azimuth, and therefore should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.
In order to solve the technical problems mentioned in the background art, the inventors innovatively devised the following field effect power transistor structure.
Referring to fig. 1, fig. 1 is a schematic structural cross-sectional view of a field effect power transistor according to an embodiment of the present application.
The field effect power transistor may include: substrate 101, P-well region 103, JFET region 104, gate oxide layer 105, polycrystalline layer 106, P-type body region 107, n+ region 108, insulating layer 109, first metal layer 110, and second metal layer 111.
JFET region 104 is located on the upper surface of substrate 101, P-well region 103 is located on both sides of JFET region 104, in this embodiment, substrate 101 is an N-type semiconductor substrate, JFET region 104 is doped with negative ions (e.g., phosphorous negative ions), and P-well region 103 is doped with positive ions (e.g., boron positive ions).
A P-type body region (P-body region) 107 is located on the upper surface of the substrate 101, and the P-type body region 107 is located between the P-well region 103 and the JFET region 104, wherein the P-type body region is doped with positive valence ions (e.g., boron positive valence ions).
N+ region 108 is located on P-type body region 107, and the n+ region is adjacent to P-well region 103. The gate oxide layer 105 is formed on one side of the upper surface of the substrate 101, the gate oxide layer 105 at least covers the JFET region 104, and the thickness of the gate oxide layer 105 is 400-1200 a.
The polycrystalline layer 106 is formed on the side of the gate oxide layer 105 away from the substrate 101, and the thickness of the polycrystalline layer 106 is not less than 5500 angstroms.
An insulating layer 109 is formed on the upper surface of the substrate 101, and the insulating layer 109 covers the polycrystalline layer 106. In the embodiment of the present application, the insulating layer 109 may be a borophospho-silicate Glass (BPSG) layer.
The first metal layer 110 is formed on one side of the upper surface of the substrate 101, the first metal layer 110 is covered on the insulating layer 109, and the first metal layer 110 contacts the P-well 103 and the n+ region. In the embodiment of the present application, the first metal layer 110 may be a metal aluminum layer.
The second metal layer 111 is formed on one side of the lower surface of the substrate 101, in this embodiment, the second metal layer 111 may include three layers of metals, such as Ti, ni and Ag, in order, and the thickness of the second metal layer 111 ranges from 100 to 10000 angstroms.
In the embodiment of the present application, the gate layer 105 is connected to a metal electrode as a gate of the field effect power transistor, the first metal layer 110 is used as a source of the field effect power transistor, and the second metal layer 111 is used as a drain of the field effect power transistor.
In the field effect power transistor provided in the above embodiment, the thickness of the gate oxide layer 105 and the polycrystalline layer 106 is thicker, so that the injected positive valence ions can be effectively prevented from entering the JFET region 104 during the manufacturing process of the P-type body region 107, and the negative valence ions in the JFET region 104 are neutralized, so that the concentration of the conductive ions in the JFET region 104 is reduced, the concentration of the conductive ions in the JFET region 104 is ensured to be stable, and accordingly, the relatively stable RDSON parameters of different field effect transistors in batches or the same batch are ensured to be maintained.
Referring to fig. 2, an embodiment of the present application further provides a method for manufacturing the above-mentioned field effect power transistor, where the method includes the following steps:
in step S201, a substrate 101 is provided.
Referring to FIG. 3A, a substrate sheet with an N-type [110] crystal orientation is provided.
In step S202, a JFET region 104 and P-well regions 103 located on both sides of the JFET region 104 are formed on the upper surface of the substrate 101.
In the embodiment of the present application, step S202 may be implemented by the following process.
First, referring to fig. 3B, an oxide layer 102 is formed on the upper surface of a substrate 101.
Specifically, hydrogen and oxygen are introduced in a high temperature environment of 1100 ℃, so that an oxide layer 102 is formed on the upper surface of the substrate 101, and the thickness of the oxide layer 102 may be 4000-5000 angstroms, preferably, the thickness of the oxide layer 102 is 4500 angstroms.
Next, referring to fig. 3C, JFET region windows and P-well region windows are formed on the oxide layer 102 by coating photoresist, photolithography, etching, photoresist removal, respectively.
Then, ions are implanted into the substrate 101 through the JFET region window and the P-well region window, respectively.
Specifically, at an implantation energy of 100Kev, phosphorus ions are implanted into the substrate 101 through the JFET region window, the amount of implantation of which may be 1-4E12; then, at an implantation energy of 80Kev, boron ions are implanted into the substrate 101 through the P-well region window, and the implantation amount of the boron ions may be 5E14-1E15.
Finally, referring to fig. 3D, a junction-pushing process is performed on the substrate 101 after ion implantation, and a JFET region 104 and a P-well region 103 are formed on the upper surface of the substrate 101.
Specifically, a junction-pushing process is performed for about 90-180 minutes in a nitrogen atmosphere at a high temperature of 1150 degrees celsius, and a JFET region 104 and a P-well region 103 are formed on the upper surface of the substrate 101.
In the above process, a JFET region window may be formed by coating photoresist, photolithography, etching, photoresist removal on the oxide layer 102, and then ions may be implanted into the substrate 101 through the JFET region window; then, forming a P well region window on the oxide layer 102 by coating photoresist, photoetching, etching and photoresist removal, and then injecting ions into the substrate 101 through the P well region window; finally, ion junction pushing treatment is carried out to obtain the JFET region 104 and the P-well region 103. It will be appreciated that the order in which the JFET region windows and P-well region windows are etched and the order in which the ions are implanted can be adjusted.
In step S203, referring to fig. 3E, a gate oxide layer 105 with a thickness ranging from 400 to 1200 angstroms is formed on the upper surface side of the substrate 101.
Specifically, the gate oxide layer 105 having a thickness in the range of 400 to 1200 angstroms is grown on the upper surface side of the substrate 101 in a growth temperature range of 950 to 1100 degrees celsius in a growth environment in which the gaseous atmosphere is pure oxygen and trichloroethylene.
In step S204, referring to fig. 3F, a polycrystalline layer 106 with a thickness of not less than 5500 angstroms is formed on a side of the gate oxide layer 105 away from the substrate 101.
Specifically, the polycrystalline layer 106 having a thickness of not less than 5500 angstroms is grown based on the side of the gate oxide layer 105 away from the substrate 101 at a growth temperature ranging from 500 to 800 degrees celsius.
In step S304 and step S305, by controlling the thicknesses of the gate oxide layer and the polycrystalline layer, the injected positive valence ions can be effectively prevented from entering the JFET region during the process of manufacturing the P-type body region, and the negative valence ions in the JFET region are neutralized, so that the concentration of the conductive ions in the JFET region is reduced, and the stability of the concentration of the conductive ions in the JFET region is ensured, thereby ensuring that different field effect transistors in different batches or the same batch maintain relatively stable RDSON parameters.
In step S205, referring to fig. 3G, a P-type body region window is formed by coating photoresist, photolithography, etching, photoresist removal on the polycrystalline layer 106 and the gate oxide layer 105, and a P-type body region 107 is formed on the upper surface of the substrate 101 by implanting ions and performing a junction pushing process.
In step S205, boron positive ions are implanted into the substrate 101 through the P-type body region window at an implantation energy of 80Kev to 120Kev, and the amount of boron positive ions may range from 2E13 to 5E13.
Specifically, during the junction pushing process of step S205, ions in the P-well region 103 continue to diffuse toward the lower surface of the substrate 101, so that the junction depth of the P-well region 103 becomes deeper, and in the embodiment of the present application, after the step S205, the junction depth of the P-well region 103 is greater than the junction depth of the P-type body region 107.
In step S206, referring to fig. 3H, an n+ region 108 is formed on the P-type body region 107, and the n+ region 108 is adjacent to the P-well region 103.
In the embodiment of the present application, step S206 may be implemented by the following process.
First, a photoresist layer is coated on the P-type body region 107.
Then, photoetching, etching and photoresist removing are carried out on the photoresist layer to obtain an N+ region window;
finally, arsenic ions with the dosage not less than 3E15 are implanted into the P-type body region 107 through the N+ region window at the implantation energy of 80-130Kev, so as to obtain an N+ region 108.
In step S206, the arsenic ion implantation dose is larger, so that it is ensured that the implanted arsenic ion can form good ohmic contact with the silicon in the substrate 101 to form good contact resistance, and stability of the RDSON parameter is ensured.
In step S207, referring to fig. 3I, an insulating layer 109 is deposited on the upper surface of the substrate 101.
In step S208, referring to fig. 3J, the insulating layer 109 on opposite sides of the upper surface of the substrate 101 is etched.
In the embodiment of the present application, step S208 may be implemented by the following process.
First, a photoresist layer is coated on the insulating layer 109.
Then, photoetching, etching and photoresist removing are carried out on the photoresist layer, and lead area windows are etched on the insulating layers 109 on two opposite sides of the upper surface of the substrate 101;
finally, the insulating layer 109 corresponding to the lead area window is etched by adopting a mode of firstly high etching power and then low etching power, so that the N+ area 108 is exposed.
In step S208, since the junction depth of the n+ region 108 is shallow, the etching amount needs to be controlled when etching the window of the lead region, and the manufacturing time of the device can be shortened by etching with high etching power and low etching power, and it can be ensured that the n+ region is not excessively etched, and the RDSON parameter of the field effect power transistor is affected.
In step S209, referring to fig. 3K, a first metal layer 110 is formed on the upper surface of the substrate 101, and the first metal layer 110 contacts the P-well 103 and the n+ region 108.
In step S210, referring to fig. 1 again, a second metal layer 111 is formed on the lower surface of the substrate 101.
Further, in the embodiment of the present application, after step S208, the method for manufacturing a field effect power transistor further includes:
removing photoresist in the lead area window by adopting a twice dry method;
removing an oxide layer and residual glue on the upper surface of the substrate 101 by adopting a mixed solution comprising an HF solution, an SC-1 solution and an SC-2 solution, wherein the SC-1 solution comprises NH with a mass ratio of 1:1:5-1:5:10 4 OH、H 2 O 2 H and H 2 The O, SC-2 solution comprises HCL and H with the mass ratio of 1:1:5-1:5:10 2 O 2 H and H 2 O。
Further, after step S209, the field effect power transistor manufacturing method further includes:
and alloying the first metal layer 110 and the substrate 101 in a working environment with a temperature of 380-450 ℃ and a gaseous environment of a mixed gas of nitrogen and hydrogen.
Through the photoresist removing operation of the steps, good alloy can be formed between the first metal layer 110 and the silicon corresponding to the lead area window, so that the RDSON parameter of the field effect power transistor is ensured to be stable, and the problem that the RDSON parameter is increased because the silicon corresponding to the first metal layer 110 and the lead area window cannot be formed into good alloy due to residual photoresist is avoided. Further, before the first metal layer 110 is fabricated, the oxide layer on the upper surface of the substrate 101 is removed by using the SC-1 solution and the SC-2 solution, so that it is ensured that the first metal layer 110 forms a good alloy with silicon corresponding to the lead area window.
In summary, embodiments of the present application provide a field effect power transistor and a method for manufacturing the same. By controlling the thickness of the gate oxide layer and the polycrystalline layer, positive valence ions (such as boron positive ions) injected into the JFET region in the manufacturing process of the P-type body region are effectively prevented from entering the JFET region, negative valence ions (such as phosphorus negative ions) in the JFET region are neutralized, the concentration of conductive ions in the JFET region is reduced, the concentration of conductive ions in the JFET region is ensured to be stable, and the RDSON parameter of the field effect power transistor is ensured to be stable. Further, when the n+ region 108 is obtained, the implantation dose of the ions with larger dose can ensure that the n+ region 108 and the substrate 101 form good ohmic contact, and simultaneously, the RDSON parameter stability of the field effect power transistor can also be ensured by controlling the etching mode of the n+ region. And then removing the photoresist twice by a dry method, and cleaning the SC-1 and SC-2 to remove the glue layer and the oxide layer, so that the RDSON parameter stability of the field effect power transistor can be further ensured. By controlling the steps in the manufacturing process, the relatively stable RDSON parameters of different field effect transistors in batches or in the same batch can be ensured.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims (10)

1. A method of fabricating a field effect power transistor, the method comprising:
providing a substrate (101);
manufacturing a JFET region (104) and P-well regions (103) positioned on two sides of the JFET region (104) on the upper surface of the substrate (101);
manufacturing a gate oxide layer (105) with the thickness ranging from 400 to 1200 angstroms on one side of the upper surface of the substrate (101);
manufacturing a polycrystalline layer (106) with the thickness not less than 5500 angstroms on the side, far away from the substrate (101), of the gate oxide layer (105);
etching the polycrystalline layer (106) and the gate oxide layer (105) to form a P-type body region window, and manufacturing a P-type body region (107) on the upper surface of the substrate (101) through ion implantation and junction pushing treatment;
-forming an n+ region (108) on the P-type body region (107), the n+ region (108) being adjacent to the P-well region (103);
depositing an insulating layer (109) on the upper surface side of the substrate (101);
etching the insulating layer (109) on opposite sides of the upper surface of the substrate (101);
manufacturing a first metal layer (110) on one side of the upper surface of the substrate (101), wherein the first metal layer (110) is in contact with the P well region (103) and the N+ region (108);
a second metal layer (111) is formed on the lower surface side of the substrate (101).
2. The method of manufacturing of claim 1, wherein manufacturing the JFET region (104) and the P-well region (103) on the upper surface of the substrate (101) comprises:
growing an oxide layer (102) with a thickness ranging from 4000 angstroms to 5000 angstroms on the upper surface of the substrate (101);
etching to form JFET region windows and P-well region windows on the oxide layer (102) respectively;
implanting ions into the substrate (101) through the JFET region window and the P-well region window, respectively;
and performing junction pushing treatment on the substrate (101) after ion implantation, and forming a JFET region (104) and a P-well region (103) on the upper surface of the substrate (101).
3. The method of manufacturing according to claim 2, wherein forming a gate oxide layer (105) having a thickness in a range of 400 to 1200 a on the upper surface side of the substrate (101) comprises:
and growing a gate oxide layer (105) with the thickness ranging from 400 to 1200 angstroms on one side of the upper surface of the substrate (101) in a growth temperature range of 950-1100 ℃ under a growth environment of pure oxygen and trichloroethylene.
4. A method of manufacturing as claimed in claim 3, characterized in that the step of forming the polycrystalline layer (106) having a thickness of not less than 5500 angstroms on the side of the gate oxide layer (105) remote from the substrate (101) comprises:
and growing a polycrystalline layer (106) with a thickness of not less than 5500 angstroms on the side of the gate oxide layer (105) away from the substrate (101) at a growth temperature ranging from 500-800 ℃.
5. The method of manufacturing of claim 4, wherein manufacturing an n+ region (108) on said P-type body region (107) comprises:
coating a photoresist layer on the P-type body region (107);
etching the photoresist layer to obtain an N+ region window;
and implanting arsenic ions with the dosage not less than 3E15 into the P-type body region (107) through the N+ region window at the implantation energy of 100-130Kev to obtain an N+ region (108).
6. The method of claim 5, wherein etching the insulating layer (109) on opposite sides of the upper surface of the substrate (101) comprises:
coating a photoresist layer on the insulating layer (109);
etching the photoresist layer, and etching lead area windows on the insulating layers (109) on two opposite sides of the upper surface of the substrate (101);
and etching the insulating layer (109) corresponding to the lead area window by adopting a mode of firstly high etching power and then low etching power, and exposing the N+ area (108).
7. The method of manufacturing of claim 6, further comprising:
removing the photoresist in the lead area window by adopting a twice dry method;
removing an oxide layer and residual glue on the upper surface of the substrate (101) by adopting a mixed solution comprising an HF solution, an SC-1 solution and an SC-2 solution, wherein the SC-1 solution comprises NH with a mass ratio of 1:1:5-1:5:10 4 OH、H 2 O 2 H and H 2 The O, SC-2 solution comprises HCL and H with the mass ratio of 1:1:5-1:5:10 2 O 2 H and H 2 O。
8. The manufacturing method according to claim 7, wherein after manufacturing the first metal layer (110) based on the upper surface side of the substrate (101), the manufacturing method further comprises:
and alloying the first metal layer (110) and the substrate (101) in a working environment with a temperature of 380-450 ℃ and a gaseous environment of a mixed gas of nitrogen and hydrogen.
9. A field effect power transistor, comprising:
a substrate (101);
the JFET region (104) is manufactured on the upper surface of the substrate (101), and the P-well regions (103) are positioned on two sides of the JFET region (104);
a P-type body region (107) formed on the upper surface of the substrate (101) and located between the P-well region (103) and the JFET region (104), wherein the P-well region (103) is doped with positive ions, and the P-type body region (107) is also doped with positive ions;
an N+ region (108) formed on the P-type body region (107) and adjacent to the P-well region (103);
the grid oxide layer (105) is manufactured on one side of the upper surface of the substrate (101), the grid oxide layer (105) at least covers the JFET region (104), and the thickness of the grid oxide layer (105) is 400-1200 angstroms;
a polycrystalline layer (106) which is manufactured on one side of the gate oxide layer (105) far away from the substrate (101), wherein the thickness of the polycrystalline layer (106) is not less than 5500 angstroms;
an insulating layer (109) formed on one side of the upper surface of the substrate (101), wherein the insulating layer (109) covers the polycrystalline layer (106);
the first metal layer (110) is manufactured on one side of the upper surface of the substrate (101), the first metal layer (110) covers the insulating layer (109), and the first metal layer (110) is in contact with the P well region (103) and the N+ region (108);
and a second metal layer (111) formed on the lower surface side of the substrate (101).
10. The field effect power transistor of claim 9, wherein the thickness of the insulating layer (109) is 8000-10000 angstroms.
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CN103000623A (en) * 2011-09-16 2013-03-27 北大方正集团有限公司 Aluminum-gate semiconductor device and manufacturing method thereof
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CN103000623A (en) * 2011-09-16 2013-03-27 北大方正集团有限公司 Aluminum-gate semiconductor device and manufacturing method thereof
CN105140283A (en) * 2015-07-28 2015-12-09 国网智能电网研究院 Silicon carbide MOSEFTs (metal-oxide-semiconductor field-effect transistors) power device and manufacturing method therefor

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