JPS6468019A - Level converting circuit - Google Patents

Level converting circuit

Info

Publication number
JPS6468019A
JPS6468019A JP62224570A JP22457087A JPS6468019A JP S6468019 A JPS6468019 A JP S6468019A JP 62224570 A JP62224570 A JP 62224570A JP 22457087 A JP22457087 A JP 22457087A JP S6468019 A JPS6468019 A JP S6468019A
Authority
JP
Japan
Prior art keywords
npn
potential
base
collector
power source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62224570A
Other languages
Japanese (ja)
Inventor
Fumio Murabayashi
Yoji Nishio
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62224570A priority Critical patent/JPS6468019A/en
Publication of JPS6468019A publication Critical patent/JPS6468019A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
    • H03K19/01806—Interface arrangements
    • H03K19/01812—Interface arrangements with at least one differential stage

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Manipulation Of Pulses (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To quickly perform level conversion, by setting the base potential of a second NPN transistor(TR) to a middle value of the potential of the signal inputted to the base input terminal of a first NPN TR. CONSTITUTION:A first NPN TR 101 and a second NPN TR 102 constitute a differential pair, and the collector of the first NPN TR 101 is directly connected to a first power source 104 and the collector of the second NPN TR 102 is connected to the first power source 104 through a first impedance element 103. Consequently, the first NPN TR 101 performs the unsaturated operation when a high level VIH of the input signal inputted to the base of the first NPN TR 101 is set to a potential lower than the potential of the first power source 104. When the base potential of the second NPN TR 102 is set to a middle value of the input potential and a first impedance element 103 and the current of a constant current circuit are so set that the potential of the collector of the second NPN TR 102 is not lower than the middle potential, the second NPN TR 102 performs the unsaturated operation also. Thus, level conversion is quickly performed.
JP62224570A 1987-09-08 1987-09-08 Level converting circuit Pending JPS6468019A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62224570A JPS6468019A (en) 1987-09-08 1987-09-08 Level converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62224570A JPS6468019A (en) 1987-09-08 1987-09-08 Level converting circuit

Publications (1)

Publication Number Publication Date
JPS6468019A true JPS6468019A (en) 1989-03-14

Family

ID=16815832

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62224570A Pending JPS6468019A (en) 1987-09-08 1987-09-08 Level converting circuit

Country Status (1)

Country Link
JP (1) JPS6468019A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0399516A (en) * 1989-09-13 1991-04-24 Toshiba Corp Level converting circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60194614A (en) * 1984-03-16 1985-10-03 Hitachi Ltd Interface circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60194614A (en) * 1984-03-16 1985-10-03 Hitachi Ltd Interface circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0399516A (en) * 1989-09-13 1991-04-24 Toshiba Corp Level converting circuit

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