JPS6481411A - Differential circuit - Google Patents
Differential circuitInfo
- Publication number
- JPS6481411A JPS6481411A JP62237197A JP23719787A JPS6481411A JP S6481411 A JPS6481411 A JP S6481411A JP 62237197 A JP62237197 A JP 62237197A JP 23719787 A JP23719787 A JP 23719787A JP S6481411 A JPS6481411 A JP S6481411A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- same time
- output
- inputted
- trs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Logic Circuits (AREA)
Abstract
PURPOSE:To constitute the titled differential circuit whose outputs go to H at the same time by clamping the base of a 1st NPN transistor(TR) at a potential of a constant reference voltage or more applied to the base of a 2nd NPN TR and holding both collectors at high level at the same time. CONSTITUTION:When H is inputted to an enable terminal 104, the common emitter of NPN TRs 101 and 102 is clamped at the H inputted to the terminal 104. Therefore, even when either H or L is inputted to an input terminal 103, TRs 101 and 102 turn on at the same time. The outputs 105 and 106, therefore, go up to the H at the same time. Namely, when the terminal 104 has high impedance, the output 105 is H and the output 106 is L on condition that the terminal 103 is H, but the output 105 is L and the output 106 is H on condition that the terminal 103 is L. When the terminal 104 is H, on the other hand, the TRs 101 and 102 turn off and the outputs 105 and 106 are both H at the same time regardless of whether the terminal 103 is H or L.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62237197A JPH0817319B2 (en) | 1987-09-24 | 1987-09-24 | 3-state circuit and output circuit using the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62237197A JPH0817319B2 (en) | 1987-09-24 | 1987-09-24 | 3-state circuit and output circuit using the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6481411A true JPS6481411A (en) | 1989-03-27 |
| JPH0817319B2 JPH0817319B2 (en) | 1996-02-21 |
Family
ID=17011809
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62237197A Expired - Fee Related JPH0817319B2 (en) | 1987-09-24 | 1987-09-24 | 3-state circuit and output circuit using the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0817319B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5827437A (en) * | 1981-08-11 | 1983-02-18 | Nec Corp | Tri-state output circuit |
| JPS61278208A (en) * | 1985-05-31 | 1986-12-09 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Cascode current switching circuit |
-
1987
- 1987-09-24 JP JP62237197A patent/JPH0817319B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5827437A (en) * | 1981-08-11 | 1983-02-18 | Nec Corp | Tri-state output circuit |
| JPS61278208A (en) * | 1985-05-31 | 1986-12-09 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Cascode current switching circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0817319B2 (en) | 1996-02-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |