JPS6465803A - Lamination of unfired sheet - Google Patents

Lamination of unfired sheet

Info

Publication number
JPS6465803A
JPS6465803A JP62223428A JP22342887A JPS6465803A JP S6465803 A JPS6465803 A JP S6465803A JP 62223428 A JP62223428 A JP 62223428A JP 22342887 A JP22342887 A JP 22342887A JP S6465803 A JPS6465803 A JP S6465803A
Authority
JP
Japan
Prior art keywords
electrode
laminated
dielectric layer
sheet
printed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62223428A
Other languages
Japanese (ja)
Inventor
Keiichi Nakao
Yasutaka Horibe
Hikoharu Okuyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62223428A priority Critical patent/JPS6465803A/en
Publication of JPS6465803A publication Critical patent/JPS6465803A/en
Pending legal-status Critical Current

Links

Landscapes

  • Thermistors And Varistors (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To conduct a highly precise alignment as well as to prevent the elongation of a dielectric layer and the shifting of electrode pitch generating in association with the drying of electrode ink by a method wherein an alignment window is provided on a part of the dielectric layer of the unfired ceramic sheet composed of a transparent film and a dielectric layer, and after the electrode has been printed, the sheet is laminated on the window. CONSTITUTION:When a multilayer ceramic substrate of electric component, a laminated ceramic capacitor, a laminated piezoelectric element and the like of electronic parts are manufactured, a transparent raw sheet 24 is composed of a dielectric layer 22a and a transparent film 23, and an electrode 25a is printed on the film 23 and the dielectric layer 22a. Also, an electrode 25b is printed on a base plate 21, and an alignment window 26 is formed by selectively removing the dielectric 22a from the sheet 24. Also, a plurality of inner electrode (not shown in the diagram) are laminated in a dielectric layer 22b, the laminated layer 22b, on which several layers of inner electrode were laminated in advance, is provided on the base plate 21, and the sheet 24 on which the electrode 25a was printed is superposed on the window 26.
JP62223428A 1987-09-07 1987-09-07 Lamination of unfired sheet Pending JPS6465803A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62223428A JPS6465803A (en) 1987-09-07 1987-09-07 Lamination of unfired sheet

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62223428A JPS6465803A (en) 1987-09-07 1987-09-07 Lamination of unfired sheet

Publications (1)

Publication Number Publication Date
JPS6465803A true JPS6465803A (en) 1989-03-13

Family

ID=16797990

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62223428A Pending JPS6465803A (en) 1987-09-07 1987-09-07 Lamination of unfired sheet

Country Status (1)

Country Link
JP (1) JPS6465803A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8426249B2 (en) 2004-12-13 2013-04-23 Panasonic Corporation Chip part manufacturing method and chip parts

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8426249B2 (en) 2004-12-13 2013-04-23 Panasonic Corporation Chip part manufacturing method and chip parts

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