JPS646547B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor photodetector having a simple and practical composite array structure that ensures isolation between elements.

Figure 1 is a schematic cross-sectional diagram showing the basic structure of a pin-type photodiode, in which an n ^- layer 2 as an i-layer is formed on an n ⁺ layer 1, which is a substrate, and a p ⁺ layer 3 is epitaxially formed on the n ^- layer 2. It has a pin structure that has been made to grow. the above
The p ⁺ layer 3 functions as a light-receiving surface, has an anti-reflection film 4 formed on its surface, and has an Al electrode lead 5 arranged around it. A p ⁺ layer 6 as a channel stopper is formed around the p ⁺ layer 3 on the n ^- layer 2, and an insulating film 7 made of SiO ₂ as a passivation is formed on its surface.
8 in the figure is a Ti--Pt--Au electrode lead formed by vapor deposition on the back surface of the p ⁺ layer 1, and a reverse bias voltage V is applied between these electrode leads 5 and 8 via a load resistor R _{L. B} is applied. Due to this reverse bias, the n ^- layer 2 becomes a depletion layer, and the n ⁺ layer 1
A high electric field is applied between the p+ layer 3 and the p ⁺ layer 3.
The light incident from the anti-reflection film 4 through the p ⁺ layer 3 is absorbed by the n ^- layer 2 to generate electron-hole pairs, and these electron-hole pairs are accelerated by the electric field. By doing so, the n ⁺ layer 1 and
p ⁺ layer 3 respectively. This generates an induced current, and a potential difference proportional to the incident light is generated across the load resistor R _L .

By the way, as shown in FIG. 2, the elements of the pin type photodiode having a composite array structure are isolated by arranging the p ⁺ layers 3 at a distance from each other. However, since the reverse bias is applied substantially uniformly to the n ^- layer 2, an electric field with a uniform lateral distribution is generated.
Therefore, carriers (holes and electrons) generated in the depletion layer not only cause a drift current accelerated by the electric field but also cause a lateral diffusion current. The above diffusion current has a distance between elements of 100μm.
In the case of silicon, which has a low current, it can be almost ignored compared to the drift current, and the crosstalk can be suppressed to about -20 dB to -30 dB.
That is, electrons and holes have their mobilities μ _o ,
μ _p , when the diffusion coefficients are D _o and D _p , D _o = kT/qμ _o , D _p = kT/qμ _p , where k: Boltzmann constant T: absolute temperature q: electron charge amount Therefore, in the range where the incident light is continuous light and its light absorption is not considered to shift with distance from the surface, the carrier diffusion becomes bipolar and crosstalk is small. However, in the vicinity of the surface of the p ⁺ −n ⁻ −n ⁺ type, only holes remain and a lateral electric field is generated, which may increase crosstalk.

For example, Japanese Patent Application Laid-open No. 54-146681, etc.
It has been proposed to reduce crosstalk by employing a semiconductor structure as shown in the figure. That is, this device structure has a p ⁺ layer 3 on the surface side as shown in FIG.
An n ⁺ layer 9 having the opposite conductivity is provided in between, so that the carriers diffusing in the lateral direction are captured by the n ⁺ layer 9 and recombined. In this case, if a positive bias is applied to the n ⁺ layer 9 compared to the p ⁺ layer 3, charge carriers (electrons and holes) will diffuse laterally due to the electric field formed by this bias. Since the material is pulled back into the element, a significant reduction in crosstalk can be expected. For example, the distance between elements
He-Ne laser beam with a wavelength of 632.8 mm as 10 μm
When a 1 μm spot is incident on the edge of an element, the crosstalk output generated in adjacent elements is -23 dB in height.
It will be about.

However, the specifications required for optical frequency analyzers include an element pitch of several μm and crosstalk of -
It is extremely severe, exceeding 50dB. In order to satisfy this requirement with the structure shown in FIG. 3, it is desirable to make the n ⁺ layer 9 as deep as possible and to combine it with the n ⁺ layer 1 which is the underlying layer. Firstly, light with a long wavelength that reaches the n ⁺ layer 1 generates carriers in the n ⁺ layer 1, but since the n ⁺ layer 1 has almost no electric field, the carriers are adjacent to each other. There is a high possibility that it will diffuse into the device and enter the depletion layer. In particular, even when diffusing carrier killer substances such as gold, the diffusion coefficient is large.
It is inappropriate to adopt this approach since it is very difficult to control the profile. Second, in order to bond the n ⁺ layer 9 and the n ⁺ layer 1, it is necessary to repeatedly perform selective diffusion of impurities and epitaxy, or to thin the n ^- layer 2 in advance. However, the former has a complicated manufacturing process and there is a large risk of contaminating the n ^- layer 2, and the latter has autodoping from the substrate (n ⁺ layer 1), so it is difficult to achieve the desired high resistance n ^- layer. There were some problems such as difficulty in obtaining 2. For this reason, it has been difficult to satisfy the specifications of the composite array structure with small pitches and small crosstalk as described above.

The present invention has been made in consideration of these circumstances, and its purpose is to provide a simple and highly practical structure that can sufficiently reduce crosstalk between elements arranged at minute pitches. An object of the present invention is to provide a semiconductor photodetector having the following characteristics.

That is, the present invention forms an electric field from the depletion layer toward the front and back sides of the substrate to effectively capture and recombine carriers, thereby preventing the carriers from flowing into the depletion layer of an adjacent element. This effectively achieves the above objectives.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 4 is a schematic sectional view showing the basic configuration of the embodiment, and FIG. 5 is a schematic diagram showing the planar configuration.
On the p ⁺ layer 11, which is the first semiconductor region of one conductivity, is the n ^- layer 1, which is the second semiconductor region of the opposite conductivity.
2 is formed. On the surface of this n ^- layer 12, a plurality of p ⁺ layers 13, which are third semiconductor regions, are formed at a predetermined pitch and spaced apart from each other.
In other words, each p ⁺ layer 13 and the p ⁺ layer 11 are the n ^- layer 12
The configuration is such that they are arranged opposite to each other via. Therefore, on the surface of the n ^- layer 12 which is the second semiconductor region, there are n ^- layers surrounding each p ⁺ layer 13.
n ⁺ with an impurity concentration approximately 10 times the impurity concentration of layer 12
A layer 14 is formed. Further, Al electrode leads 15 and 16 are provided independently on the surface of this n ⁺ layer 14 and the surface of each of the p ⁺ layers 13,
Further, a Ti--Pt--Au electrode lead 17 is provided on the back surface of the p ⁺ layer 11 (substrate), which is the first semiconductor region. Each of the p ⁺ layers 13 forms a light receiving element, and an antireflection film 18, which will be described later, is coated on the surface thereof. In the figure, reference numeral 19 denotes an insulating layer made of SiO ₂ or the like, which is provided with contact holes for electrically separating the electrode leads 15 and 16 and connecting each electrode lead 15 and 16 to the n ⁺ layer 14 and the p ⁺ layer 13. be.

Therefore, a reverse bias voltage V _B is applied between each of the electrode leads 15 and 16 via a load resistor R _L , and each of the p ⁺ layer 13, the n ^- layer 12 and the n ⁺ layer 1
A p ⁺ −n ⁻ −n ⁺ type photodiode (PD) is formed between the 4 and 4. Further, ^{an electrode} lead 15,
A reverse bias V _c is applied through 17, each forming a diode.

By the way, the n ^- layer 12 is, for example, a substrate.
It is formed by epitaxial growth on the p ⁺ layer 11, or alternatively, the bulk of a high-resistance n-type wafer is used as the n ^- layer 12, and both sides thereof are doped to form the p ⁺ layers 11 and 13. The structure shown in FIG. 4 may be obtained by doing this. Now, from the viewpoint of increasing the density of devices, the width of the n ⁺ layer 14 is as narrow as possible to the extent necessary for isolation between devices.
Further, it is desirable that the layer be formed deeper than the p ⁺ layer 13. At the same time, the reverse bias V _c
is applied so that the depletion layer (indicated by a broken line in the figure) formed in the n ^- layer 12 is formed so wide as to reach from the p ⁺ layer 11 to the lower end of the n ⁺ layer 14. In addition, the reverse bias V _B needs to be set low so that the depletion layer extending from the p ⁺ layer 13 in the n ^- layer 12 does not punch through between the p ⁺ layer 11 and the p ⁺ layer 13. There is.

Thus, if such a bias setting is applied, the holes generated by absorbing the incident light in the depletion layer will reach the p ⁺ layer 11 and the p ⁺ layer 13 of each element due to their drift, and both n between depletion layers ^-
Holes generated in layer 12 enter one of the depletion layers mentioned above, reach p ⁺ layer 11 or 13, and recombine.
Or the carrier diffused in the horizontal direction is n ⁺ layer 1
4 and will be reunited. Therefore, the adverse effects of the lateral diffusion of carriers in the depletion layer or the diffusion of carriers generated in the lower layer are almost eliminated. As a result, signals are almost completely separated between each element, and a photodiode having an array structure with very low crosstalk can be obtained. In particular, when the element is made of silicon, the absorption coefficient is large for short wavelength light with a wavelength λ of 0.7 μm or less, so the effect is large. In addition, sufficient effects can be achieved even for long wavelength light by making the device depletion layer thicker.

Now, the surface of the p ⁺ layer 13 becomes the light incident surface,
If an improvement in the quantum efficiency η is expected, it is necessary that there is no optical shielding. Furthermore, it is desirable that the surface be non-reflective in order to improve the quantum efficiency η and reduce crosstalk caused by scattered light. Therefore, for example, Koji Ishiguro's ``Optics'' Kyoritsu Zensho,
PP169-170 (Published on August 10, 1962: 1st edition, 13th edition)
As introduced in et al., the refractive index of the p ⁺ layer 13 is set to n
Then, a transparent film having a refractive index equal to the square root of n ₀ (=√) and a thickness of λ ₀ /4n ₀ with respect to the wavelength λ ₀ of the light to be detected is coated as the anti-reflection film 18. Good. By forming such an anti-reflection film 18, it is possible to satisfy the non-reflection condition, improve the quantum efficiency η of the device, and prevent the adverse effects of scattered light.

Furthermore, since the n ⁺ layer 14 is intended to promote carrier recombination and improve the isolation characteristics between elements, it is desirable that the impurity (donor) density be as high as possible. Therefore, if impurities are implanted using PSG (phosphosilicate glass) or POCl ₃ (phosphorus oxychloride) as a diffusion source, a concentration of about 10 ¹⁹ to 10 ²⁰ cm ^-3 can be easily obtained, and the above requirements ( specifications). Furthermore, if the n ⁺ layer 14 is formed by ion implantation, there is an advantage that lateral diffusion can be reduced, and the depth of the n ⁺ layer 14 can be controlled by varying the acceleration voltage. There are advantages such as Furthermore, setting a sufficiently deep depth can be easily achieved by alternately repeating the impurity doping and epitaxy several times, making it easy to realize a photodetector with this structure and requiring exceptional manufacturing efficiency. It does not require any ingenuity.
Note that if the ratio of the impurity concentrations of the n ⁺ layer 14 and the n ^- layer 12 is set to at least 10 times or more, the effect will be noticeable. Thus, a semiconductor photodetector with a simple structure is realized in which the pitch between elements can be reduced and the elements can be sufficiently separated.

By the way, it is also possible to apply the structure shown in FIG. 3 to the present invention as shown in FIG. 6, for example. That is, in FIG. 3, the p ^- layer 10 can be formed by ion implantation or the like. In other words, it can be applied particularly when the p ⁺ layer 13 is thin and the electric field is concentrated around it and there is a possibility of causing dielectric breakdown. For example, make the p ^- layer 10 deeper than the p ⁺ layer 13,
In addition, if it is formed shallower than the n ⁺ layer 14, it can be electrically isolated from adjacent elements, and the junction surface can be used as the interface between the n ⁺ layer 14 and the p ^- layer 10. Since there are no steep joints, it is possible to improve the absolute voltage. Therefore, the sixth
As shown in the figure, a p ^- layer 10 as a fifth semiconductor region is formed between a p ⁺ layer 13 and an n ⁺ layer 14, and its impurity concentration is higher than that of the n ^- layer 12, and the p ⁺ layer 1
If it is set to at least 1/5 or less compared to 3, the same effect as in the previous embodiment can be expected. Also p ^- layer 10
It is sufficient to apply the reverse bias V _c to such an extent that the depletion layer therein reaches the periphery of the p ⁺ layer 13 .

Moreover, the present invention can be modified and implemented as follows. In the previous embodiment, it has been described that the bias conditions are set to such an extent that the depletion layer of the n ^- layer 12 does not punch through between the p ⁺ layer 11 and the p ⁺ layer 13. In this case, the region between the two depletion layers functions as a path for the signal current of each element, and may act as a series resistance to reduce the output signal. Therefore, as shown in FIG. 7, for example, it is useful to lower the resistance by increasing the impurity concentration in the region between the depletion layers by at least five times or more. That is, in order to increase the impurity concentration in the region 20 between the depletion layers, for example, phosphorus (P) such as arsenic (As) or antimony (Sb) is added to the surface of the wafer on which the n ^- layer 12 is epitaxially grown. After that, selective doping of phosphorus (P) and epitaxy are alternately repeated in a predetermined region to form an n ⁺ layer 14, and then p ⁺ This structure can be constructed by forming the layer 13 by doping, but the p ^- layer 10 may also be formed by doping if necessary.

If the structure shown in Fig. 7 is adopted, 2
Since the extension of the two depletion layers reaches the above-mentioned high impurity region and decreases, the above-mentioned punch-through is effectively prevented. Therefore, crosstalk between adjacent elements can be significantly reduced without destroying element functions due to punch-through, and the effect is very large.

Note that each of the above embodiments uses a photodiode (PD).
Although the present invention has been described with reference to FIG. 8, it can also be applied to a phototransistor. 8th
In the figure, 21 is an n ⁺ layer provided in the p layer 13, and the n ⁺ layer 21, the p ⁺ layer 13, and the n ⁺ layer 14 form an n ⁺ −
A p ⁺ −n ⁺ type phototransistor is constructed.
In addition to configuring a phototransistor in this manner, it is of course also possible to monolithically form an amplifier element, a switching element, a modulation element, etc. on the same pellet at the same time. It is also possible to apply the present invention to a photodetector having a structure in which a waveguide for incident light is formed on a pellet, and the arrangement and configuration of the plurality of light receiving elements may be determined according to specifications. Of course, it is also possible to use semiconductor specifications with opposite polarity. In short, the present invention can be implemented with various modifications without departing from the gist thereof.

As detailed above, the semiconductor structure according to the present invention can narrow the arrangement pitch between elements,
Moreover, crosstalk between elements can be sufficiently reduced. Moreover, the element can be given wavelength selectivity for incident light, and in particular, in the case of a Si element, the peak of detection sensitivity can be set on the short wavelength side. Furthermore, in special cases, the characteristics can be brought close to the visibility curve, which is a great advantage. Therefore, it is useful as a sensor for image file memory, facsimile transmitter, etc., and can also be applied to spectrophotometers, etc., and has extremely great practical advantages, and it is possible to effectively achieve the above-mentioned purpose. can.

[Brief explanation of drawings]

Fig. 1 is a schematic diagram showing the basic configuration of a pin type photodiode, Fig. 2 is a diagram showing a simple example of isolation between elements, and Fig. 3 is a configuration diagram showing an example of a conventional structure with isolation between elements. FIG. 4 is a cross-sectional configuration diagram showing an embodiment of the present invention, FIG. 5 is a plan configuration diagram of the embodiment,
FIGS. 6 to 8 are cross-sectional configuration diagrams showing other embodiments of the present invention. 11... p ⁺ layer (first semiconductor region), 12...
n ^- layer (second semiconductor region), 13... p ⁺ layer (third
semiconductor region), 14... n ⁺ layer (fourth semiconductor region), 15, 16, 17... electrode lead, 18...
...Antireflection film, 19...Insulating layer, 20...High concentration region (depletion interlayer region), 21...n ⁺ layer, 10...
p ^-layer (high concentration region).

Claims (1)

[Scope of Claims] 1: a second semiconductor region of opposite conductivity formed on a first semiconductor region of one conductivity; a plurality of third semiconductor regions arranged on the surface of the semiconductor region and having the surface as a light-receiving surface; a fourth semiconductor region provided on the surface of the second semiconductor region surrounding each of the third semiconductor regions; A semiconductor photodetector characterized in that a reverse bias is applied between each of the third semiconductor region and the fourth semiconductor region. 2 The third semiconductor region has at least its surface a _refractive index n p approximately equal to the square root of the refractive index of the third semiconductor region, and has a refractive index n _p approximately equal to the square root of the refractive index of the third semiconductor region, and approximately λ _p /
The semiconductor photodetector according to claim 1, which is coated with a transparent film having a thickness of _4np . 3 The fourth semiconductor region is 10 times larger than the second semiconductor region.
Claim 1, which has an impurity concentration twice or more, and is formed by alternately repeating impurity doping and epitaxy in the second semiconductor region.
Semiconductor photodetector described in Section 1. 4 The second semiconductor region has the same conductivity as the third semiconductor region in a region deeper than the third semiconductor region and shallower than the fourth semiconductor region between the third and fourth semiconductor regions on the surface thereof. Sexual impurity concentration is 1/
2. The semiconductor photodetector according to claim 1, wherein five or less layers are formed. 5. The semiconductor photodetector according to claim 1, wherein a plurality of the third semiconductor regions are formed in an island shape on the surface of the second semiconductor region to form an array structure.