JPS6464077A - Linear interpolation arithmetic unit - Google Patents

Linear interpolation arithmetic unit

Info

Publication number
JPS6464077A
JPS6464077A JP62221448A JP22144887A JPS6464077A JP S6464077 A JPS6464077 A JP S6464077A JP 62221448 A JP62221448 A JP 62221448A JP 22144887 A JP22144887 A JP 22144887A JP S6464077 A JPS6464077 A JP S6464077A
Authority
JP
Japan
Prior art keywords
register
input
coefficient
magnification
interpolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62221448A
Other languages
Japanese (ja)
Inventor
Yoshihiro Igawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Facom Corp
Original Assignee
Fuji Facom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Facom Corp filed Critical Fuji Facom Corp
Priority to JP62221448A priority Critical patent/JPS6464077A/en
Publication of JPS6464077A publication Critical patent/JPS6464077A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T3/00—Geometric image transformation in the plane of the image
    • G06T3/40—Scaling the whole image or part thereof
    • G06T3/4007—Interpolation-based scaling, e.g. bilinear interpolation

Abstract

PURPOSE:To set an optional magnification except integers by updating a coefficient for interpolation and an input address based on the result of addition of the magnification and the coefficient for interpolation. CONSTITUTION:An input image element string L containing N image elements is magnified to Z times and then converted into an output image element string M containing NZ image elements. In this case, 1/Z is set at a magnification register 1 so that the most significant bit is equal to the first decimal position bit as an initializing action. Then a coefficient holding register 2 is cleared to zero and at the same time the address of an image element A is set at an input address register 5. Data on the image elements A and B are led to 1st and 2nd input data registers 7 and 9 while the the input addresses are updated. The linear interpolation 4 is carried out by means of both data A and B of the registers 7 and 9 as well as a coefficient for interpolation. Then an output address register 12 is increased for updating of the output addresses. The contents of the register 2 are added 3 with the contents of a magnification register 1. When the result of the addition 3 is larger than 1, a carry signal is turned on and the decimal part of the result of the addition 3 is held by the register 2.
JP62221448A 1987-09-04 1987-09-04 Linear interpolation arithmetic unit Pending JPS6464077A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62221448A JPS6464077A (en) 1987-09-04 1987-09-04 Linear interpolation arithmetic unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62221448A JPS6464077A (en) 1987-09-04 1987-09-04 Linear interpolation arithmetic unit

Publications (1)

Publication Number Publication Date
JPS6464077A true JPS6464077A (en) 1989-03-09

Family

ID=16766894

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62221448A Pending JPS6464077A (en) 1987-09-04 1987-09-04 Linear interpolation arithmetic unit

Country Status (1)

Country Link
JP (1) JPS6464077A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61140271A (en) * 1984-12-12 1986-06-27 Fuji Xerox Co Ltd Image magnifying and reducing circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61140271A (en) * 1984-12-12 1986-06-27 Fuji Xerox Co Ltd Image magnifying and reducing circuit

Similar Documents

Publication Publication Date Title
DE69504135D1 (en) Device for updating program counters
JPS6472278A (en) Computer-aided drafting system
JPS57207958A (en) Data correcting device
GB2317466B (en) Data processing condition code flags
EP0884674A3 (en) Arithmetic and logic unit with accumulator and parallel register
JPS54117646A (en) Computer
TW232060B (en) Image processing apparatus
JPS54122043A (en) Electronic computer
JPS6464077A (en) Linear interpolation arithmetic unit
JPS54127628A (en) Crt display unit containing extension code display circuit
EP0169030A3 (en) Data processing circuit for calculating either a total sum or a total product of a series of data at a high speed
JPS5573060A (en) Copying machine
KR940015793A (en) Binary multiplication implemented by less modified existing hardware
JPS54152820A (en) Data processor
JPS57203279A (en) Information processing device
JPS57121749A (en) Fraction computer
SU1273918A1 (en) Adding-subtracting device
JPS6486271A (en) Accumulator
JPS57111667A (en) Data processing circuit
JPS54155733A (en) Page-address update processing system
JPS564920A (en) Digital filter
JPS6454528A (en) Processor
JPS5771045A (en) Digital mulitplier
JPS5525162A (en) Electronic desk calculator
JPS564844A (en) Information processor