JPS6463810A - Processing device for output signal of incremental type encoder - Google Patents

Processing device for output signal of incremental type encoder

Info

Publication number
JPS6463810A
JPS6463810A JP22010687A JP22010687A JPS6463810A JP S6463810 A JPS6463810 A JP S6463810A JP 22010687 A JP22010687 A JP 22010687A JP 22010687 A JP22010687 A JP 22010687A JP S6463810 A JPS6463810 A JP S6463810A
Authority
JP
Japan
Prior art keywords
counter
incremental
signal
pulse
decremental
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22010687A
Other languages
Japanese (ja)
Inventor
Kaoru Inoue
Kazuyoshi Morimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mazda Motor Corp
Original Assignee
Mazda Motor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mazda Motor Corp filed Critical Mazda Motor Corp
Priority to JP22010687A priority Critical patent/JPS6463810A/en
Publication of JPS6463810A publication Critical patent/JPS6463810A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain an accurate feedback information by a construction wherein a count operation of a second incremental/decremental counter is stopped by a carrying signal or a carry down signal of its own. CONSTITUTION:A first incremental/decremental counter 5 counting pulses of a first pulse-train signal obtained from an encoder 2 is employed as an upper counter, while a second incremental/decremental counter 12 counting pulses of a second pulse-train signal being an output of a PLL circuit 6 and N- multiplied gradually is employed as a lower counter. A carry up signal and a carry down signal outputted from this lower counter 12 are not connected to the upper counter 5, and the lower counter 12 is initialized by the edge of each pulse of the first pulse-train signal. In addition, the operation of the second incremental/decremental counter 12 stops when it counts pules in the number of N. According to this constitution, an accurate position feedback information is obtained even when the locking of the PLL circuit 6 is removed.
JP22010687A 1987-09-04 1987-09-04 Processing device for output signal of incremental type encoder Pending JPS6463810A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22010687A JPS6463810A (en) 1987-09-04 1987-09-04 Processing device for output signal of incremental type encoder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22010687A JPS6463810A (en) 1987-09-04 1987-09-04 Processing device for output signal of incremental type encoder

Publications (1)

Publication Number Publication Date
JPS6463810A true JPS6463810A (en) 1989-03-09

Family

ID=16746006

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22010687A Pending JPS6463810A (en) 1987-09-04 1987-09-04 Processing device for output signal of incremental type encoder

Country Status (1)

Country Link
JP (1) JPS6463810A (en)

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