JPS6462731A - Microprogram controller - Google Patents

Microprogram controller

Info

Publication number
JPS6462731A
JPS6462731A JP22061887A JP22061887A JPS6462731A JP S6462731 A JPS6462731 A JP S6462731A JP 22061887 A JP22061887 A JP 22061887A JP 22061887 A JP22061887 A JP 22061887A JP S6462731 A JPS6462731 A JP S6462731A
Authority
JP
Japan
Prior art keywords
micro
control memory
held
microprogram
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22061887A
Other languages
Japanese (ja)
Inventor
Takayuki Noguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP22061887A priority Critical patent/JPS6462731A/en
Publication of JPS6462731A publication Critical patent/JPS6462731A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To easily cope with a design change, etc. by controlling and realizing a loading operation of a micro-instruction to a first control memory, by using a microprogram held in a second control memory. CONSTITUTION:When a micro-instruction to be executed is not held on the first control memory 2, outputs of a comparator 4 are discordant and a start micro-logical address of a microprogram held in a second control memory 7 is supplied to a second register 6. When the second register 6 holds this start micro-logical address, the head micro-instruction of the microprogram is read out of the second control memory 7, and a series of micro-instructions are executed. In such a case, a loading circuit 9 is controlled by execution of the microprogram held in the second control memory 7, a real address on a main storage device 5 in which a micro-instruction corresponding to a micro-logical address held in a first register 1 is stored is derived, and by this address, the micro-instruction corresponding to the micro-logical address is read out, and written to a first control register 2.
JP22061887A 1987-09-02 1987-09-02 Microprogram controller Pending JPS6462731A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22061887A JPS6462731A (en) 1987-09-02 1987-09-02 Microprogram controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22061887A JPS6462731A (en) 1987-09-02 1987-09-02 Microprogram controller

Publications (1)

Publication Number Publication Date
JPS6462731A true JPS6462731A (en) 1989-03-09

Family

ID=16753794

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22061887A Pending JPS6462731A (en) 1987-09-02 1987-09-02 Microprogram controller

Country Status (1)

Country Link
JP (1) JPS6462731A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010070918A1 (en) 2008-12-18 2010-06-24 旭化成イーマテリアルズ株式会社 Ablation layer, photosensitive resin structure, and method for producing relief printing plate using the photosensitive resin structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010070918A1 (en) 2008-12-18 2010-06-24 旭化成イーマテリアルズ株式会社 Ablation layer, photosensitive resin structure, and method for producing relief printing plate using the photosensitive resin structure

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