JPS6460132A - Duo-binary signal demodulating circuit - Google Patents

Duo-binary signal demodulating circuit

Info

Publication number
JPS6460132A
JPS6460132A JP62217000A JP21700087A JPS6460132A JP S6460132 A JPS6460132 A JP S6460132A JP 62217000 A JP62217000 A JP 62217000A JP 21700087 A JP21700087 A JP 21700087A JP S6460132 A JPS6460132 A JP S6460132A
Authority
JP
Japan
Prior art keywords
duo
charge pump
charge
signal
sampling time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62217000A
Other languages
Japanese (ja)
Inventor
Yasuhiko Shioe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Electric Corp filed Critical Yokogawa Electric Corp
Priority to JP62217000A priority Critical patent/JPS6460132A/en
Publication of JPS6460132A publication Critical patent/JPS6460132A/en
Pending legal-status Critical Current

Links

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To output an optimum sampling time by supplying a signal for a correction so as to cancel an error voltage generated in a charge pump according to the transition condition of an element timing clock. CONSTITUTION:A charge correcting circuit 19 is provided which outputs correcting signals 213 and 214 to instruct a charge and a discharge to a charge pump 107 when a phase deciding device 106 deviates, in depending on a signal pattern, from an ideal charge pump control in which an element timing clock 206 and the optimum sampling time coincide at the time of inputting the output signal of a level deciding device 104 and the element timing clock 206. Thus, a duo-binary signal demodulating circuit can be obtained in which a sampling clock can be maintained in the optimum sampling time without depending on the transmitting signal pattern.
JP62217000A 1987-08-31 1987-08-31 Duo-binary signal demodulating circuit Pending JPS6460132A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62217000A JPS6460132A (en) 1987-08-31 1987-08-31 Duo-binary signal demodulating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62217000A JPS6460132A (en) 1987-08-31 1987-08-31 Duo-binary signal demodulating circuit

Publications (1)

Publication Number Publication Date
JPS6460132A true JPS6460132A (en) 1989-03-07

Family

ID=16697246

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62217000A Pending JPS6460132A (en) 1987-08-31 1987-08-31 Duo-binary signal demodulating circuit

Country Status (1)

Country Link
JP (1) JPS6460132A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5289278A (en) * 1991-02-21 1994-02-22 Plessey Semiconductors Limited Duo-binary and/or binary data slicer
WO2007037312A1 (en) * 2005-09-28 2007-04-05 Nec Corporation Clock reproduction device and method
WO2007111035A1 (en) * 2006-03-24 2007-10-04 Nec Corporation Data receiver and semiconductor integrated circuit having that data receiver

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5289278A (en) * 1991-02-21 1994-02-22 Plessey Semiconductors Limited Duo-binary and/or binary data slicer
WO2007037312A1 (en) * 2005-09-28 2007-04-05 Nec Corporation Clock reproduction device and method
US8184738B2 (en) 2005-09-28 2012-05-22 Nec Corporation Clock reproducing apparatus and method
WO2007111035A1 (en) * 2006-03-24 2007-10-04 Nec Corporation Data receiver and semiconductor integrated circuit having that data receiver

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