JPS6459550A - System for controlling automatic bypass of message - Google Patents
System for controlling automatic bypass of messageInfo
- Publication number
- JPS6459550A JPS6459550A JP62217509A JP21750987A JPS6459550A JP S6459550 A JPS6459550 A JP S6459550A JP 62217509 A JP62217509 A JP 62217509A JP 21750987 A JP21750987 A JP 21750987A JP S6459550 A JPS6459550 A JP S6459550A
- Authority
- JP
- Japan
- Prior art keywords
- output
- message
- destination device
- abnormality
- bypass
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE:To utilize an output destination device at a maximum, by outputting a message to a corresponding output destination device by an input/output control part according to an actual device number table when receiving a message output request by a user program, and outputting a following message to another output destination device when an actual device is set at a state impossible to be used. CONSTITUTION:When the message output request is issued from the user program A to, for example, the output destination device 103-1, an input/output controller IOP transmits the request to the output device 103-1. It is assumed that a certain kind of abnormality is generated while the output destination device 103-1 is issuing the message of the user program A. The input/output controller IOP finds the actual device number (103-2) that is a bypass destination by referring to the actual device number table 102 which detects the abnormality, and performs a bypass processing to output the message of the user program A to the actual device number. When the abnormality is generated in the output destination device 103-2, the message is outputted to a bypass destination device after next. Thus, it is possible to perform the switching of automatic bypass destination rapidly for the generation of the abnormality in the output destination device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62217509A JPS6459550A (en) | 1987-08-31 | 1987-08-31 | System for controlling automatic bypass of message |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62217509A JPS6459550A (en) | 1987-08-31 | 1987-08-31 | System for controlling automatic bypass of message |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6459550A true JPS6459550A (en) | 1989-03-07 |
Family
ID=16705346
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62217509A Pending JPS6459550A (en) | 1987-08-31 | 1987-08-31 | System for controlling automatic bypass of message |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6459550A (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5457923A (en) * | 1977-10-18 | 1979-05-10 | Fujitsu Ltd | Faulty input/output device switching processing system in on-line system |
JPS5790734A (en) * | 1980-11-28 | 1982-06-05 | Toshiba Corp | Switching system of input/output device |
JPS6011954A (en) * | 1983-06-30 | 1985-01-22 | Fujitsu Ltd | Terminal device |
-
1987
- 1987-08-31 JP JP62217509A patent/JPS6459550A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5457923A (en) * | 1977-10-18 | 1979-05-10 | Fujitsu Ltd | Faulty input/output device switching processing system in on-line system |
JPS5790734A (en) * | 1980-11-28 | 1982-06-05 | Toshiba Corp | Switching system of input/output device |
JPS6011954A (en) * | 1983-06-30 | 1985-01-22 | Fujitsu Ltd | Terminal device |
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