JPS6458181A - Binary differential signal correction circuit - Google Patents

Binary differential signal correction circuit

Info

Publication number
JPS6458181A
JPS6458181A JP62214524A JP21452487A JPS6458181A JP S6458181 A JPS6458181 A JP S6458181A JP 62214524 A JP62214524 A JP 62214524A JP 21452487 A JP21452487 A JP 21452487A JP S6458181 A JPS6458181 A JP S6458181A
Authority
JP
Japan
Prior art keywords
differential signal
area
correction
picture elements
binarized differential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62214524A
Other languages
Japanese (ja)
Inventor
Takahiko Hisaki
Yutaka Nakatani
Yoshio Nagashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP62214524A priority Critical patent/JPS6458181A/en
Publication of JPS6458181A publication Critical patent/JPS6458181A/en
Pending legal-status Critical Current

Links

Landscapes

  • Compression Or Coding Systems Of Tv Signals (AREA)

Abstract

PURPOSE:To contrive to improve the accuracy of extracting a background picture elements by correcting a level of a difference signal being at a threshold value or below in the moving area in a retarded binarized differential signal before correction into a part over the threshold value while the retarded binarized differential signal before correction and the result of discrimination by an area discrimination means. CONSTITUTION:An area correction circuit 130 executes the correction processing to a retarded binarized differential signal before correction to be entered. An area discrimination circuit 150 discriminates it as a consecutive moving area block where picture elements whose binarized differential signal is significant '1' being the result of correction of picture elements whose binarized differential signal before correction is significant '1' are consecutive. Then the moving area block number for each scanning line and the block number of consecutive significant picture element '1' in the binarized differential signal in each block are counted and an area correction circuit 130 outputs the result as a form being referenced. However, '1' represents picture elements in the copy area. Thus, the moving part is extracted correctly even in a picture element with a small differential signal between frames.
JP62214524A 1987-08-28 1987-08-28 Binary differential signal correction circuit Pending JPS6458181A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62214524A JPS6458181A (en) 1987-08-28 1987-08-28 Binary differential signal correction circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62214524A JPS6458181A (en) 1987-08-28 1987-08-28 Binary differential signal correction circuit

Publications (1)

Publication Number Publication Date
JPS6458181A true JPS6458181A (en) 1989-03-06

Family

ID=16657149

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62214524A Pending JPS6458181A (en) 1987-08-28 1987-08-28 Binary differential signal correction circuit

Country Status (1)

Country Link
JP (1) JPS6458181A (en)

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