JPS645523U - - Google Patents

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Publication number
JPS645523U
JPS645523U JP9983687U JP9983687U JPS645523U JP S645523 U JPS645523 U JP S645523U JP 9983687 U JP9983687 U JP 9983687U JP 9983687 U JP9983687 U JP 9983687U JP S645523 U JPS645523 U JP S645523U
Authority
JP
Japan
Prior art keywords
gain
circuit
gain setting
switch
switch elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9983687U
Other languages
English (en)
Other versions
JPH0619207Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987099836U priority Critical patent/JPH0619207Y2/ja
Publication of JPS645523U publication Critical patent/JPS645523U/ja
Application granted granted Critical
Publication of JPH0619207Y2 publication Critical patent/JPH0619207Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Control Of Amplification And Gain Control (AREA)

Description

【図面の簡単な説明】
第１図は本考案の一実施例を示した回路図、第
２図は従来例を示した回路図である。 １１ａ〜１１ｃ：バイパス用のアナログスイツ
チ、１５ａ〜１５ｃ：利得設定用のアナログスイ
ツチ、１８ａ〜１８ｃ：利得設定抵抗、１２，１
６，１９，２０：トランジスタ、１３，１７，２
１，２２，２３：抵抗。

Claims (1)

  1. 【実用新案登録請求の範囲】 エミツタフオロア回路と次段のベース接地増幅
    回路との間に、複数の利得設定抵抗を前記回路間
    に選択的に接続して回路利得を設定する複数の利
    得設定スイツチ素子を前記利得設定抵抗毎に設け
    た利得制御回路に於いて、 前記利得設定スイツチ素子の各々に、スイツチ
    オフ状態で逆にオンしてスイツチ出力側を別途設
    けたエミツタフオロア回路のエミツタ電位に接続
    する複数のバイパス用スイツチ素子を設けたこと
    を特徴とする利得制御回路。
JP1987099836U 1987-06-29 1987-06-29 利得制御回路 Expired - Lifetime JPH0619207Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987099836U JPH0619207Y2 (ja) 1987-06-29 1987-06-29 利得制御回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987099836U JPH0619207Y2 (ja) 1987-06-29 1987-06-29 利得制御回路

Publications (2)

Publication Number Publication Date
JPS645523U true JPS645523U (ja) 1989-01-12
JPH0619207Y2 JPH0619207Y2 (ja) 1994-05-18

Family

ID=31327364

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987099836U Expired - Lifetime JPH0619207Y2 (ja) 1987-06-29 1987-06-29 利得制御回路

Country Status (1)

Country Link
JP (1) JPH0619207Y2 (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5014226B2 (ja) * 2008-03-28 2012-08-29 日本電信電話株式会社 可変利得増幅器
JP5640725B2 (ja) * 2010-12-20 2014-12-17 三菱電機株式会社 電力増幅器

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56131217A (en) * 1976-10-29 1981-10-14 Tektronix Inc Variable attenuator

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56131217A (en) * 1976-10-29 1981-10-14 Tektronix Inc Variable attenuator

Also Published As

Publication number Publication date
JPH0619207Y2 (ja) 1994-05-18

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