JPS6454924A - Clock pulse generating circuit - Google Patents

Abstract

PURPOSE:To minimize the timing error without increasing the frequency of a basic clock by generating polyphase clocks from a stable basic clock pulse, and selecting one out of them. CONSTITUTION:(N+1)-phase of clock pulses are generated from a basic clock FO from a basic clock generating section 1 by a polyphase clock generating section 2 and fed to a selection control section 3. The control section 3 receiving a signal to be processed selects alternatively a clock pulse defining a time closest to the timing at which the signal to be processed coming asynchronously with the clock pulse is to be subject to holding. The selected clock pulse is used as the basic clock pulse. Since the phase difference of the clock pulses subject to poly phase processing is 1/N+1 with respect to that of the basic clock pulse, the timing error is reduced to 1/N without multiplying the basic clock frequency by a factor of M.