JPS5665320A - Processor for digital signal - Google Patents
Processor for digital signalInfo
- Publication number
- JPS5665320A JPS5665320A JP14167279A JP14167279A JPS5665320A JP S5665320 A JPS5665320 A JP S5665320A JP 14167279 A JP14167279 A JP 14167279A JP 14167279 A JP14167279 A JP 14167279A JP S5665320 A JPS5665320 A JP S5665320A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- pbk
- counter
- synchronizing signal
- block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE: To make it secure to allot signals to subblocks by controlling a clock counter by detecting the block-synchronizing signal of the 1st subblock in one field of reproduced data.
CONSTITUTION: This processor is equipped with circuit 50 that counts a clock from PLL321 on the basis of signal REV having a prescribed phase relation with the initial time point of the main block of reproduced data to generate 51 window pulse WP, outputs block-synchronizing signal BK of the 1st subblock as it is when it is within the width of WP, and obtains alternate pulse MP in the middle of the width of WP to obtain synchronizing signal PBK. Then, counter 61 is made to self- correlation to signal BK by the output CN1, and counter 62 is controlled by signals SR and PBK to restore absent signal BK by its outputs CN2 and PBK, eliminating influence of a mixed false pulse.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14167279A JPS5665320A (en) | 1979-10-31 | 1979-10-31 | Processor for digital signal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14167279A JPS5665320A (en) | 1979-10-31 | 1979-10-31 | Processor for digital signal |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5665320A true JPS5665320A (en) | 1981-06-03 |
Family
ID=15297504
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14167279A Pending JPS5665320A (en) | 1979-10-31 | 1979-10-31 | Processor for digital signal |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5665320A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1985000066A1 (en) * | 1983-06-14 | 1985-01-03 | Sony Corporation | Synchronizing circuit |
DE3630375A1 (en) * | 1985-09-10 | 1987-03-12 | Mitsubishi Electric Corp | DATA RECORDING PROCEDURE |
-
1979
- 1979-10-31 JP JP14167279A patent/JPS5665320A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1985000066A1 (en) * | 1983-06-14 | 1985-01-03 | Sony Corporation | Synchronizing circuit |
AU583251B2 (en) * | 1983-06-14 | 1985-01-11 | Sony Corporation | Synchronizing circuit |
DE3630375A1 (en) * | 1985-09-10 | 1987-03-12 | Mitsubishi Electric Corp | DATA RECORDING PROCEDURE |
NL8602260A (en) * | 1985-09-10 | 1987-04-01 | Mitsubishi Electric Corp | METHOD FOR RECORDING DATA. |
US4774701A (en) * | 1985-09-10 | 1988-09-27 | Mitsubishi Denki Kabushiki Kaisha | Data recording method with improved synchronization recovery |
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