JPS6453656A - Communicating control clock margin generating circuit - Google Patents
Communicating control clock margin generating circuitInfo
- Publication number
- JPS6453656A JPS6453656A JP62210966A JP21096687A JPS6453656A JP S6453656 A JPS6453656 A JP S6453656A JP 62210966 A JP62210966 A JP 62210966A JP 21096687 A JP21096687 A JP 21096687A JP S6453656 A JPS6453656 A JP S6453656A
- Authority
- JP
- Japan
- Prior art keywords
- clock
- clock margin
- margin
- generating circuit
- control clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE:To simplify a clock margin evaluation test by providing an input output interface and a program controllable clock margin generating means at a communication control clock margin generating device. CONSTITUTION:A clock signal outputted from a time division exchanging switch module 1 is supplied through an input interface 3 to a clock variable part 4, and here, in accordance with the switch operation or a control signal inputted from a program control part 6, a clock margin is set. Simultaneously, at the time of the program control, a displaying signal to display the setting conditions is outputted and displayed from the control part 6 to a monitoring part 7. The output of the clock variable part 4 is supplied through an output interface 5 to a communication control part 8 which is a tested device and a clock margin evaluation test is executed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62210966A JPS6453656A (en) | 1987-08-24 | 1987-08-24 | Communicating control clock margin generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62210966A JPS6453656A (en) | 1987-08-24 | 1987-08-24 | Communicating control clock margin generating circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6453656A true JPS6453656A (en) | 1989-03-01 |
Family
ID=16598066
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62210966A Pending JPS6453656A (en) | 1987-08-24 | 1987-08-24 | Communicating control clock margin generating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6453656A (en) |
-
1987
- 1987-08-24 JP JP62210966A patent/JPS6453656A/en active Pending
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