JPS6453242A - Memory device - Google Patents

Memory device

Info

Publication number
JPS6453242A
JPS6453242A JP20989287A JP20989287A JPS6453242A JP S6453242 A JPS6453242 A JP S6453242A JP 20989287 A JP20989287 A JP 20989287A JP 20989287 A JP20989287 A JP 20989287A JP S6453242 A JPS6453242 A JP S6453242A
Authority
JP
Japan
Prior art keywords
memory bank
significant
following
data bus
bytes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20989287A
Other languages
Japanese (ja)
Inventor
Hirofumi Suda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Electric Corp filed Critical Yokogawa Electric Corp
Priority to JP20989287A priority Critical patent/JPS6453242A/en
Publication of JPS6453242A publication Critical patent/JPS6453242A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To designate an optional address and to access said address regardless of the number of data bytes to be accessed, by allocating the memory bank output to the most significant or least significant byte of a data bus to a memory bank having no idle area and then allocating the following memory bank outputs successively to the following positions of the data bus. CONSTITUTION:The memory bank output (byte unit) corresponding to a designated address given from a CPU to the most significant or least significant byte of a data bus DB having the width equal to plural bytes is allocated to the memory banks 10-13 having no idle area. Hereafter the following bank outputs are successively allocated to the following positions of the bus DB respectively. Thus it is possible to designate an optional address regardless of the number of data bytes to be accessed and to access the banks 10-13.
JP20989287A 1987-08-24 1987-08-24 Memory device Pending JPS6453242A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20989287A JPS6453242A (en) 1987-08-24 1987-08-24 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20989287A JPS6453242A (en) 1987-08-24 1987-08-24 Memory device

Publications (1)

Publication Number Publication Date
JPS6453242A true JPS6453242A (en) 1989-03-01

Family

ID=16580374

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20989287A Pending JPS6453242A (en) 1987-08-24 1987-08-24 Memory device

Country Status (1)

Country Link
JP (1) JPS6453242A (en)

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