JPS6453182A - Radar signal processor - Google Patents

Radar signal processor

Info

Publication number
JPS6453182A
JPS6453182A JP62209961A JP20996187A JPS6453182A JP S6453182 A JPS6453182 A JP S6453182A JP 62209961 A JP62209961 A JP 62209961A JP 20996187 A JP20996187 A JP 20996187A JP S6453182 A JPS6453182 A JP S6453182A
Authority
JP
Japan
Prior art keywords
stages
delay circuits
delay
varied
transmission line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62209961A
Other languages
Japanese (ja)
Inventor
Akio Izumi
Toshio Mitsui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62209961A priority Critical patent/JPS6453182A/en
Publication of JPS6453182A publication Critical patent/JPS6453182A/en
Pending legal-status Critical Current

Links

Landscapes

  • Radar Systems Or Details Thereof (AREA)

Abstract

PURPOSE:To obtain the best threshold value for suppressing a clutter contained in a radar video by varying positively the number of stages of delay circuits forming a signal transmission line. CONSTITUTION:Delay circuits 12F and 13F which constitute the signal transmission line 10' across a center cell 1 are variable delay circuits and a magnification device 25F which constitutes a total averaging circuit 20' with adders 21 and 22, a subtracter 23, an integrator 24, etc., is a variable magnification device whose magnification 1/M is varied and set according to the number M of delay stages. A high cutoff frequency varies in proportion to the reciprocal of the number M of delay stages, so the number M of stages is varied to realize control the setting of the high cutoff frequency. Consequently, invariably constant warning probability can be maintained without being affected by the property of the clutter contained in the radar video.
JP62209961A 1987-08-24 1987-08-24 Radar signal processor Pending JPS6453182A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62209961A JPS6453182A (en) 1987-08-24 1987-08-24 Radar signal processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62209961A JPS6453182A (en) 1987-08-24 1987-08-24 Radar signal processor

Publications (1)

Publication Number Publication Date
JPS6453182A true JPS6453182A (en) 1989-03-01

Family

ID=16581537

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62209961A Pending JPS6453182A (en) 1987-08-24 1987-08-24 Radar signal processor

Country Status (1)

Country Link
JP (1) JPS6453182A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0392783A (en) * 1989-09-05 1991-04-17 Nec Corp Radar signal processor
JP2006200932A (en) * 2005-01-18 2006-08-03 Mitsubishi Electric Corp Radar signal processing system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0392783A (en) * 1989-09-05 1991-04-17 Nec Corp Radar signal processor
JP2006200932A (en) * 2005-01-18 2006-08-03 Mitsubishi Electric Corp Radar signal processing system

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