JPS533760A - Viriable active group delay equalizer - Google Patents

Viriable active group delay equalizer

Info

Publication number
JPS533760A
JPS533760A JP7804076A JP7804076A JPS533760A JP S533760 A JPS533760 A JP S533760A JP 7804076 A JP7804076 A JP 7804076A JP 7804076 A JP7804076 A JP 7804076A JP S533760 A JPS533760 A JP S533760A
Authority
JP
Japan
Prior art keywords
active group
group delay
viriable
delay equalizer
equalizer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7804076A
Other languages
Japanese (ja)
Inventor
Yuzo Fukushi
Yoshiji Furuya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7804076A priority Critical patent/JPS533760A/en
Publication of JPS533760A publication Critical patent/JPS533760A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/04—Control of transmission; Equalising
    • H04B3/14—Control of transmission; Equalising characterised by the equalising network used
    • H04B3/146—Control of transmission; Equalising characterised by the equalising network used using phase-frequency equalisers
    • H04B3/148—Control of transmission; Equalising characterised by the equalising network used using phase-frequency equalisers variable equalisers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Networks Using Active Elements (AREA)

Abstract

PURPOSE:The base grounded transistor circuit of which the impedance is low is connected to the output terminal of a unit active group delay equalizer to obtain the output from its collector, thereby simplifying the circuit constitution and preventing the loss of delay characteristics.
JP7804076A 1976-06-30 1976-06-30 Viriable active group delay equalizer Pending JPS533760A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7804076A JPS533760A (en) 1976-06-30 1976-06-30 Viriable active group delay equalizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7804076A JPS533760A (en) 1976-06-30 1976-06-30 Viriable active group delay equalizer

Publications (1)

Publication Number Publication Date
JPS533760A true JPS533760A (en) 1978-01-13

Family

ID=13650705

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7804076A Pending JPS533760A (en) 1976-06-30 1976-06-30 Viriable active group delay equalizer

Country Status (1)

Country Link
JP (1) JPS533760A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4890170A (en) * 1987-08-20 1989-12-26 Pioneer Electronic Corporation Waveform equalization circuit for a magnetic reproducing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4890170A (en) * 1987-08-20 1989-12-26 Pioneer Electronic Corporation Waveform equalization circuit for a magnetic reproducing device

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