JPS645177U - - Google Patents
Info
- Publication number
- JPS645177U JPS645177U JP9822187U JP9822187U JPS645177U JP S645177 U JPS645177 U JP S645177U JP 9822187 U JP9822187 U JP 9822187U JP 9822187 U JP9822187 U JP 9822187U JP S645177 U JPS645177 U JP S645177U
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- test object
- control unit
- voltage
- card
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 claims description 8
- 238000005259 measurement Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Tests Of Electronic Circuits (AREA)
Description
第１図は本考案に係る半導体試験装置の一実施
例を示す構成図、第２図は動作フローを示す図、
第３図ないし第４図は動作を説明するためのデー
タおよびパターンを示す図、第５図はカウンタブ
ロツクの構成を示す図である。
ＣＣ……ホスト・コンピユータ、ＣＵ……コン
トロール・ユニツト、ＤＵＴ……試験対象物、Ｓ
Ｃ……ソース系の計測カード、ＭＳ……メジヤー
系の計測カード、ＰＧＣ……パターン・ジエネレ
ータ・カード、５０……カウンタブロツク、５１
……メモリ、５２……マイクロプロセツサ、５３
……バス、５４ａ，５４ｂ，５４ｃ，５４ｄ……
カウンタ、５５……プログラマブル・デバイダ、
５６……基準クロツク発生器。
FIG. 1 is a configuration diagram showing an embodiment of a semiconductor testing device according to the present invention, and FIG. 2 is a diagram showing an operation flow.
3 and 4 are diagrams showing data and patterns for explaining the operation, and FIG. 5 is a diagram showing the configuration of the counter block. CC...Host computer, CU...Control unit, DUT...Test object, S
C...Source system measurement card, MS...Measure system measurement card, PGC...Pattern generator card, 50...Counter block, 51
...Memory, 52 ...Microprocessor, 53
...Bus, 54a, 54b, 54c, 54d...
Counter, 55...programmable divider,
56...Reference clock generator.
Claims (1)
・ユニツトから試験対象物に所定パターンの電圧
または電流を印加し、その際に試験対象物から出
力される電圧または電流をコントロール・ユニツ
トで測定し、その測定結果に基づきホスト・コン
ピユータで試験対象物の良否を判別することがで
きるように構成された半導体試験装置において、 前記コントロール・ユニツトを、 テーブルに予め設定したパターン・データを
順次に出力する任意パターンのスイープモードと
、 複数個の固定のパターンが定められ、各固定
パターンに対して予め設定された時間幅パラメー
タから目的の複数の固定パターンを同時に生成す
る固定パターンのスイープモードを備えたパター
ン・ジエネレータ・カードと、 このパターン・ジエネレータ・カードから出力
された一つまたは複数のパターンに応じて一つま
たは複数の電圧または電流波形の出力を試験対象
物に印加するソース系の計測カード より構成したことを特徴とする半導体試験装置
。[Claims for Utility Model Registration] A control unit applies a predetermined pattern of voltage or current to a test object under the control of a host computer, and at that time the voltage or current output from the test object is controlled by the control unit. In a semiconductor test equipment configured to allow a host computer to determine the quality of the test object based on the measurement results, the control unit sequentially sends pattern data set in advance to a table. There are two types of sweep mode: an arbitrary pattern sweep mode that outputs an arbitrary pattern, and a fixed pattern sweep mode where multiple fixed patterns are defined and multiple target fixed patterns are simultaneously generated from the time width parameter set in advance for each fixed pattern. A pattern generator card equipped with a pattern generator card, and a source system that applies one or more voltage or current waveform outputs to the test object in response to one or more patterns output from the pattern generator card. A semiconductor testing device characterized by comprising a card.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9822187U JPS645177U (en) | 1987-06-26 | 1987-06-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9822187U JPS645177U (en) | 1987-06-26 | 1987-06-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS645177U true JPS645177U (en) | 1989-01-12 |
Family
ID=31324291
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9822187U Pending JPS645177U (en) | 1987-06-26 | 1987-06-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS645177U (en) |
-
1987
- 1987-06-26 JP JP9822187U patent/JPS645177U/ja active Pending
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