JPS6451530A - Controller for micro program - Google Patents

Controller for micro program

Info

Publication number
JPS6451530A
JPS6451530A JP20752287A JP20752287A JPS6451530A JP S6451530 A JPS6451530 A JP S6451530A JP 20752287 A JP20752287 A JP 20752287A JP 20752287 A JP20752287 A JP 20752287A JP S6451530 A JPS6451530 A JP S6451530A
Authority
JP
Japan
Prior art keywords
memory
block
micro
control
micro program
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20752287A
Other languages
Japanese (ja)
Inventor
Atsushi Iwata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP20752287A priority Critical patent/JPS6451530A/en
Publication of JPS6451530A publication Critical patent/JPS6451530A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To use control memories more effectively by loading the constitution blocks of a micro program which exist on a large scale memory on a small scale buffer memory in units of a block so as to execute it. CONSTITUTION:If a load control part 10 is started by a load request in the case of totally non-coincident, which is outputted from an OR gate 9, the control part 10 reads block number including a micro instruction for execution from the high-order bit 3a of a micro logical address which is held in an address register 3 and reads the block from a main memory 1. If the output of a comparator (one out of 70-73) corresponding to resident instruction registers where '1' stands in high-order bits 50a-53a shows non-coincident, the control memory corresponding to the resident instruction register where the high-order bits 50a-53a show '0' is selected, and the block which has been read from the main memory 1 is loaded on the control memory. Thus, a resident instruction corresponding to the content of the micro program can be given to the control memory.
JP20752287A 1987-08-21 1987-08-21 Controller for micro program Pending JPS6451530A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20752287A JPS6451530A (en) 1987-08-21 1987-08-21 Controller for micro program

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20752287A JPS6451530A (en) 1987-08-21 1987-08-21 Controller for micro program

Publications (1)

Publication Number Publication Date
JPS6451530A true JPS6451530A (en) 1989-02-27

Family

ID=16541114

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20752287A Pending JPS6451530A (en) 1987-08-21 1987-08-21 Controller for micro program

Country Status (1)

Country Link
JP (1) JPS6451530A (en)

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