JPS6451327U - - Google Patents

Info

Publication number
JPS6451327U
JPS6451327U JP14550087U JP14550087U JPS6451327U JP S6451327 U JPS6451327 U JP S6451327U JP 14550087 U JP14550087 U JP 14550087U JP 14550087 U JP14550087 U JP 14550087U JP S6451327 U JPS6451327 U JP S6451327U
Authority
JP
Japan
Prior art keywords
output
output circuit
transistors
drive capacity
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14550087U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14550087U priority Critical patent/JPS6451327U/ja
Publication of JPS6451327U publication Critical patent/JPS6451327U/ja
Pending legal-status Critical Current

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  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の出力回路の回路図。第2図a
〜dは本考案の出力回路を構成する基本セルを示
す図。第3図a,bは本考案により構成する目的
の回路例を示す図。第4図a,bは本考案を構成
する基本セルのパターン例を示す図。第5図及び
第6図は本考案の出力回路のパターン例を示す図
。 1……ゲート入力信号、2……基本セル、3…
…出力信号、4……Pchトランジスタ及び電源
とのコンタクト、5……ゲート入力、6……Pc
hドレイン、7……ゲートと入力信号のコンタク
ト、8……Nchドレイン、9……Nchトラン
ジスタ及び電源とのコンタクト、10……入力配
線、11……ドライバー入力配線又は補助ドライ
バー出力配線、12……出力配線、13……予備
の基本セル。
FIG. 1 is a circuit diagram of the output circuit of the present invention. Figure 2a
-D are diagrams showing basic cells constituting the output circuit of the present invention. FIGS. 3a and 3b are diagrams showing an example of a target circuit constructed according to the present invention. FIGS. 4a and 4b are diagrams showing examples of basic cell patterns constituting the present invention. 5 and 6 are diagrams showing examples of patterns of the output circuit of the present invention. 1... Gate input signal, 2... Basic cell, 3...
...Output signal, 4...Contact with Pch transistor and power supply, 5...Gate input, 6...Pc
h drain, 7... Contact between gate and input signal, 8... Nch drain, 9... Contact with Nch transistor and power supply, 10... Input wiring, 11... Driver input wiring or auxiliary driver output wiring, 12... ...Output wiring, 13...Spare basic cell.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] トランジスタにより構成され、入力信号を受け
、出力電圧又は出力電流を提供する出力回路にお
いて、単位駆動能力を有するトランジスターを複
数段、並列接続される事により必要な駆動能力を
実現する事を特徴とする出力回路。
In an output circuit that is composed of transistors and receives an input signal and provides an output voltage or output current, the required drive capacity is achieved by connecting multiple stages of transistors with unit drive capacity in parallel. Output circuit.
JP14550087U 1987-09-24 1987-09-24 Pending JPS6451327U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14550087U JPS6451327U (en) 1987-09-24 1987-09-24

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14550087U JPS6451327U (en) 1987-09-24 1987-09-24

Publications (1)

Publication Number Publication Date
JPS6451327U true JPS6451327U (en) 1989-03-30

Family

ID=31414146

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14550087U Pending JPS6451327U (en) 1987-09-24 1987-09-24

Country Status (1)

Country Link
JP (1) JPS6451327U (en)

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