JPS6450144A - Memory checking system - Google Patents

Memory checking system

Info

Publication number
JPS6450144A
JPS6450144A JP62206965A JP20696587A JPS6450144A JP S6450144 A JPS6450144 A JP S6450144A JP 62206965 A JP62206965 A JP 62206965A JP 20696587 A JP20696587 A JP 20696587A JP S6450144 A JPS6450144 A JP S6450144A
Authority
JP
Japan
Prior art keywords
data
memory
normal value
train
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62206965A
Other languages
Japanese (ja)
Inventor
Tetsuo Maeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62206965A priority Critical patent/JPS6450144A/en
Publication of JPS6450144A publication Critical patent/JPS6450144A/en
Pending legal-status Critical Current

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  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To detect an abnormal state of a memory by adding each data at every line and comparing it with a normal value, shifting a data of each address of the memory, adding it at every line, comparing it with the normal value, and deciding it to be normal, only when both of them have coincided with the normal value. CONSTITUTION:A data 100 which has been read out of a memory is inputted to the first decision train generating means 1 and the second decision train generating means 2. The means 1 derives the sum of every line of the data, derives a decision train consisting of the sum of each line and inputs it to a comparing means 3. The means 3 compares the input and the train consisting of a normal value, and H, and L are outputted to an AND circuit 5, when both have coincided, and at the time of discrepancy, respectively. The means 2 shifts the input data and makes out a decision train Y, and outputs it to a comparing means 4. The means 4 compares the train consisting of the normal value which has been derived in advance, and the decision train Y, and H, and L are outputted to the circuit 5, when both have coincided, and at the time of discrepancy, respectively. The circuit 5 takes AND of the means 3, 4, and a final deciding signal for deciding whether the memory is normal or abnormal is outputted.
JP62206965A 1987-08-20 1987-08-20 Memory checking system Pending JPS6450144A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62206965A JPS6450144A (en) 1987-08-20 1987-08-20 Memory checking system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62206965A JPS6450144A (en) 1987-08-20 1987-08-20 Memory checking system

Publications (1)

Publication Number Publication Date
JPS6450144A true JPS6450144A (en) 1989-02-27

Family

ID=16531933

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62206965A Pending JPS6450144A (en) 1987-08-20 1987-08-20 Memory checking system

Country Status (1)

Country Link
JP (1) JPS6450144A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0713875A (en) * 1993-06-28 1995-01-17 Nec Corp Method for checking write to rom

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0713875A (en) * 1993-06-28 1995-01-17 Nec Corp Method for checking write to rom

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