JPS6449986A - Testing circuit for digital circuit - Google Patents

Testing circuit for digital circuit

Info

Publication number
JPS6449986A
JPS6449986A JP62205190A JP20519087A JPS6449986A JP S6449986 A JPS6449986 A JP S6449986A JP 62205190 A JP62205190 A JP 62205190A JP 20519087 A JP20519087 A JP 20519087A JP S6449986 A JPS6449986 A JP S6449986A
Authority
JP
Japan
Prior art keywords
operation state
group
groups
low level
grp0
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62205190A
Other languages
Japanese (ja)
Inventor
Makoto Aihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62205190A priority Critical patent/JPS6449986A/en
Publication of JPS6449986A publication Critical patent/JPS6449986A/en
Pending legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To confirm and set data with a short pattern number by performing only the confirmation and setting of output data of one group of flip-flops independently. CONSTITUTION:In a normal operation state, an operation state selection signal SEL is held at high level. At this time, the enable signal ENB0 of a group GRP0 falls to a low level. The enable signals ENB1 of groups GRP1-GRP7 fall to the low level and all the groups are ready to operate. In a shift operation state, the operation state select SEL is held at the low level and one of the groups GRP0, GRP1...GRP7 is set with group select signals GRPSEL0, GRPSEL 1, and GRPSEL2. Therefore, only the group GRP0 is ready to perform shift operation. Consequently, the confirmation and setting of data are performed with the short pattern number.
JP62205190A 1987-08-20 1987-08-20 Testing circuit for digital circuit Pending JPS6449986A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62205190A JPS6449986A (en) 1987-08-20 1987-08-20 Testing circuit for digital circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62205190A JPS6449986A (en) 1987-08-20 1987-08-20 Testing circuit for digital circuit

Publications (1)

Publication Number Publication Date
JPS6449986A true JPS6449986A (en) 1989-02-27

Family

ID=16502894

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62205190A Pending JPS6449986A (en) 1987-08-20 1987-08-20 Testing circuit for digital circuit

Country Status (1)

Country Link
JP (1) JPS6449986A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60154173A (en) * 1984-01-25 1985-08-13 Toshiba Corp Scanning type logical circuit
JPS60171545A (en) * 1984-02-17 1985-09-05 Nec Corp Logical integrated circuit
JPS6199875A (en) * 1984-10-23 1986-05-17 Toshiba Corp Scan system logical circuit
JPS61193082A (en) * 1985-02-21 1986-08-27 Nec Corp Scan path system of lsi

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60154173A (en) * 1984-01-25 1985-08-13 Toshiba Corp Scanning type logical circuit
JPS60171545A (en) * 1984-02-17 1985-09-05 Nec Corp Logical integrated circuit
JPS6199875A (en) * 1984-10-23 1986-05-17 Toshiba Corp Scan system logical circuit
JPS61193082A (en) * 1985-02-21 1986-08-27 Nec Corp Scan path system of lsi

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