JPS6449450A - Header detecting method - Google Patents

Header detecting method

Info

Publication number
JPS6449450A
JPS6449450A JP20711487A JP20711487A JPS6449450A JP S6449450 A JPS6449450 A JP S6449450A JP 20711487 A JP20711487 A JP 20711487A JP 20711487 A JP20711487 A JP 20711487A JP S6449450 A JPS6449450 A JP S6449450A
Authority
JP
Japan
Prior art keywords
header
register
inspection
circuit
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20711487A
Other languages
Japanese (ja)
Inventor
Yoshiki Iwasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Victor Company of Japan Ltd
Original Assignee
Victor Company of Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Company of Japan Ltd filed Critical Victor Company of Japan Ltd
Priority to JP20711487A priority Critical patent/JPS6449450A/en
Publication of JPS6449450A publication Critical patent/JPS6449450A/en
Pending legal-status Critical Current

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  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

PURPOSE:To correctly detect a header and to improve transmission efficiency, by performing error inspection after detecting the code of the header, and shifting a reading position in a memory sequentially until the correct result of the error inspection is obtained. CONSTITUTION:When a shift register 3 reads data of one block, a switch 2 is connected to (b) side, then, the output terminal Q of the register 3 is connected to the input terminal of the register. Simultaneously, the data is supplied from the terminal Q of the register 3 to a header detection circuit 5 and a CRC inspection circuit 6 in synchronism with a clock signal. When the header detection circuit 5 detects the same code as that of the header, the circuit 6 is reset, and CRC inspection is started. When an error exists in the result of the CRC inspection, the register 3 shifts again a readout data position by every bit until the circuit 5 finds out the same code as that of the header. In such a way, when the correct result of the CRC inspection is obtained, the data is sent from a multiplexer 8 via a port 9.
JP20711487A 1987-08-20 1987-08-20 Header detecting method Pending JPS6449450A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20711487A JPS6449450A (en) 1987-08-20 1987-08-20 Header detecting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20711487A JPS6449450A (en) 1987-08-20 1987-08-20 Header detecting method

Publications (1)

Publication Number Publication Date
JPS6449450A true JPS6449450A (en) 1989-02-23

Family

ID=16534427

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20711487A Pending JPS6449450A (en) 1987-08-20 1987-08-20 Header detecting method

Country Status (1)

Country Link
JP (1) JPS6449450A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5112706A (en) * 1974-07-20 1976-01-31 Nippon Electric Co
JPS5614743A (en) * 1979-07-18 1981-02-13 Matsushita Electric Ind Co Ltd Signal transmitter
JPS59221047A (en) * 1983-05-30 1984-12-12 Victor Co Of Japan Ltd Synchronizing signal detecting circuit for digital signal transmission

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5112706A (en) * 1974-07-20 1976-01-31 Nippon Electric Co
JPS5614743A (en) * 1979-07-18 1981-02-13 Matsushita Electric Ind Co Ltd Signal transmitter
JPS59221047A (en) * 1983-05-30 1984-12-12 Victor Co Of Japan Ltd Synchronizing signal detecting circuit for digital signal transmission

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