JPS6449198A - Sample-hold circuit - Google Patents
Sample-hold circuitInfo
- Publication number
- JPS6449198A JPS6449198A JP62205029A JP20502987A JPS6449198A JP S6449198 A JPS6449198 A JP S6449198A JP 62205029 A JP62205029 A JP 62205029A JP 20502987 A JP20502987 A JP 20502987A JP S6449198 A JPS6449198 A JP S6449198A
- Authority
- JP
- Japan
- Prior art keywords
- sample
- hold
- sampling
- time
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
PURPOSE:To accurately obtain a sample-hold output by varying the charging impedance of a sample-hold capacitor at the time of a sample-holding mode and controlling its charging speed. CONSTITUTION:At the time of sample-hold, a signal is inputted to an input terminal 1. A sample is specified by a sample-hold pulse. A switch means S constituted of a resistor R1 and an operational amplifier 2 is turned on by the instruction. Under said status, the capacitor C starts to be charged through a variable resistor R. The resistor R is controlled by an impedance variable circuit 5. The control width is small at the initial period of sampling and is gradually increased from the sample mode up to the end of sampling. Thereby, the charging speed to the capacitor C is high at the initial time and is decelerated at the end of sampling. Consequently, an accurate sample/hold output not influenced by amplifier noise which may be generated at the time of switching from the sampling mode to the holding mode can be obtained and outputted from an output terminal 3.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62205029A JPS6449198A (en) | 1987-08-20 | 1987-08-20 | Sample-hold circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62205029A JPS6449198A (en) | 1987-08-20 | 1987-08-20 | Sample-hold circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6449198A true JPS6449198A (en) | 1989-02-23 |
Family
ID=16500260
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62205029A Pending JPS6449198A (en) | 1987-08-20 | 1987-08-20 | Sample-hold circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6449198A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02268523A (en) * | 1989-04-11 | 1990-11-02 | Nec Corp | Digital/analog converter |
WO2004001763A1 (en) * | 2002-06-25 | 2003-12-31 | Zarlink Semiconductor (U.S.) Inc. | Sample and hold circuit |
ITFO20110009A1 (en) * | 2011-08-12 | 2013-02-13 | Marco Bennati | SYSTEM AND METHOD OF REDUCTION OF NOISE IN CHAMPIONSHIP AMPLIFIERS. |
-
1987
- 1987-08-20 JP JP62205029A patent/JPS6449198A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02268523A (en) * | 1989-04-11 | 1990-11-02 | Nec Corp | Digital/analog converter |
WO2004001763A1 (en) * | 2002-06-25 | 2003-12-31 | Zarlink Semiconductor (U.S.) Inc. | Sample and hold circuit |
US7026804B2 (en) | 2002-06-25 | 2006-04-11 | Zarlink Semiconductor (U.S.) Inc. | Sample and hold circuit |
ITFO20110009A1 (en) * | 2011-08-12 | 2013-02-13 | Marco Bennati | SYSTEM AND METHOD OF REDUCTION OF NOISE IN CHAMPIONSHIP AMPLIFIERS. |
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