JPS6442962A - Signal receiver - Google Patents

Abstract

PURPOSE:To prevent the deterioration in the reception sensitivity by means of one discrimination circuit by adding a received and recovered clock signal to an input of the discrimination circuit using a partial response converter and converting the reception signal in terms of AC and applying binary identification as an identification level. CONSTITUTION:The constitution is adopted such that a phase and level adjustment circuit 16 is added to a conventional receiver 6. Then a reference value (identification level) of a reception signal identified by a binary identifying device 8 is deviated to a positive or negative optimum identification level with respect to zero at a time when the eye pattern is a tri-state value and the optimum identification level is made to zero at a time when the eye pattern is a binary value. The phase and amplitude of a reception (recovered) clock fc15 from a 1/2 frequency divider 14 are adjusted by a phase and level adjustment circuit 16 depending on the identified reference value and the result is inputted to a binary identifying device 8. Thus, the optimum identification is applied in the binary and ternary eye pattern to avoid the deterioration of the reception sensitivity.