JPS6441059A - Memory controller - Google Patents

Abstract

PURPOSE:To realize a simple and highly reliable inter-processor communication system by transmitting the communication data together with a communication request to the processor set in a communication destination address. CONSTITUTION:A selected selector 3107 transmits a fixed address stored in a fixed address register 3105 and sets it at an address transmission register 3109 to use it as the writing address of the writing data to a memory 2. While a selector 3108 sets the writing command of the memory 2 stored in a writing command register 3106 at a memory access command register 3110 and transmits the command to a signal line 1e as a memory writing access request of the memory 2. The writing data set at a port writing data register 3103 is set at a memory writing data transmission registers 3111 and then written into the memory 2 via a signal line 1f. The communication destination address and the communication data set at a port address register 3101 are sent to a processor 12 indicated by the communication destination address together with an inter-processor communication request via a signal line 1g.