JPS6437641A - Intermediate buffer control system - Google Patents

Intermediate buffer control system

Info

Publication number
JPS6437641A
JPS6437641A JP62194850A JP19485087A JPS6437641A JP S6437641 A JPS6437641 A JP S6437641A JP 62194850 A JP62194850 A JP 62194850A JP 19485087 A JP19485087 A JP 19485087A JP S6437641 A JPS6437641 A JP S6437641A
Authority
JP
Japan
Prior art keywords
bytes
block
access
msu
transferred
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62194850A
Other languages
Japanese (ja)
Other versions
JPH0685154B2 (en
Inventor
Tsuyoshi Motokurumada
Koichi Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62194850A priority Critical patent/JPH0685154B2/en
Publication of JPS6437641A publication Critical patent/JPS6437641A/en
Publication of JPH0685154B2 publication Critical patent/JPH0685154B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To attain efficient memory access by reducing the main storage access priority of a move-in address register when the value of an access counter reaches a previously determined value. CONSTITUTION:A local buffer storage (LBS) consists of 32 bytes/block, a groval buffer storage (GBS) consists of 64 bytes/block. When an access request is received in the order of block fetching storing at the time of transferring each 8 bytes between a main storage unit (MSU) a main control unit (MCU), 32 bytes (8 bytes X 4) in the first half are transferred from the MSU and then the succeeding storing processing is executed before transferring 32 bytes in the latter half, and during the succeeding idle time, the above-mentioned 32 bytes in the latter half are controlled so as to be transferred.
JP62194850A 1987-08-04 1987-08-04 Intermediate buffer control method Expired - Fee Related JPH0685154B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62194850A JPH0685154B2 (en) 1987-08-04 1987-08-04 Intermediate buffer control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62194850A JPH0685154B2 (en) 1987-08-04 1987-08-04 Intermediate buffer control method

Publications (2)

Publication Number Publication Date
JPS6437641A true JPS6437641A (en) 1989-02-08
JPH0685154B2 JPH0685154B2 (en) 1994-10-26

Family

ID=16331319

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62194850A Expired - Fee Related JPH0685154B2 (en) 1987-08-04 1987-08-04 Intermediate buffer control method

Country Status (1)

Country Link
JP (1) JPH0685154B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04156635A (en) * 1990-10-19 1992-05-29 Fujitsu Ltd Block read address generation system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04156635A (en) * 1990-10-19 1992-05-29 Fujitsu Ltd Block read address generation system

Also Published As

Publication number Publication date
JPH0685154B2 (en) 1994-10-26

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees