JPS6436065A - Bipolar type semiconductor device - Google Patents

Bipolar type semiconductor device

Info

Publication number
JPS6436065A
JPS6436065A JP62190086A JP19008687A JPS6436065A JP S6436065 A JPS6436065 A JP S6436065A JP 62190086 A JP62190086 A JP 62190086A JP 19008687 A JP19008687 A JP 19008687A JP S6436065 A JPS6436065 A JP S6436065A
Authority
JP
Japan
Prior art keywords
grooves
isolation regions
finess
inter
depth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62190086A
Other languages
Japanese (ja)
Inventor
Masahiro Takagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62190086A priority Critical patent/JPS6436065A/en
Publication of JPS6436065A publication Critical patent/JPS6436065A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/10DRAM devices comprising bipolar components

Landscapes

  • Bipolar Transistors (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To repair defective writing and to realize finess of an element and to improve reliability in wiring by flattening, by burying an insulating substance and polycrystalline silicon held in insulation and the like into grooves formed in a semiconductor substrate. CONSTITUTION:In a structure of grooves composing element isolation regions 4 and inter-cell isolation regions 8, insulation films 4a and 8a such as oxide films are formed respectively on inner surfaces of the grooves, and spaces formed between the grooves are filled with polycrystalline silicon materials 4b and 8b. When element isolation regions in a bipolar transistor or the like are composed of deep grooves 4 and the inter-cell isolation regions are composed of grooves 8 smaller in depth than the grooves 4, widthwise spreading of the isolation regions can be reduced to realize finess of the element. These grooves 4 and 8 can be formed sufficiently deep compared with depth of impurities in the elements and the cells, dispersion in breakdown strength and bit interference due to a parasitic pnpn between the cells can be prevented to make good writing possible. Further flatness on the isolation region can be realized, and aluminum wirings or the like can be prevented from being disconnected.
JP62190086A 1987-07-31 1987-07-31 Bipolar type semiconductor device Pending JPS6436065A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62190086A JPS6436065A (en) 1987-07-31 1987-07-31 Bipolar type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62190086A JPS6436065A (en) 1987-07-31 1987-07-31 Bipolar type semiconductor device

Publications (1)

Publication Number Publication Date
JPS6436065A true JPS6436065A (en) 1989-02-07

Family

ID=16252133

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62190086A Pending JPS6436065A (en) 1987-07-31 1987-07-31 Bipolar type semiconductor device

Country Status (1)

Country Link
JP (1) JPS6436065A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5614445A (en) * 1991-04-02 1997-03-25 Fuji Electric Co., Ltd. Method of dicing semiconductor wafer
EP0823736A2 (en) * 1996-08-05 1998-02-11 Sifu Hu Vertical bipolar transistor and method of manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5614445A (en) * 1991-04-02 1997-03-25 Fuji Electric Co., Ltd. Method of dicing semiconductor wafer
EP0823736A2 (en) * 1996-08-05 1998-02-11 Sifu Hu Vertical bipolar transistor and method of manufacturing the same
EP0823736A3 (en) * 1996-08-05 1999-07-21 Sifu Hu Vertical bipolar transistor and method of manufacturing the same

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