JP2785542B2 - Semiconductor diffusion layer resistance - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resistance of a semiconductor diffusion layer, and more particularly to a resistance of a semiconductor diffusion layer in which a leakage current due to surface inversion between diffusion layers is prevented.

[0002]

2. Description of the Related Art Semiconductor diffused layer resistors used in bipolar integrated circuits and the like are superior in absolute accuracy and relative accuracy to polycrystalline semiconductor layer resistors, and are particularly indispensable for linear circuits. FIG. 3A is a top view of a diffusion layer resistor used in a conventional bipolar integrated circuit.
FIG. 3B is a cross-sectional view taken along line AA ₁ in FIG. 3
01 is a P ⁻ type semiconductor substrate, 302 is an N ⁺ type buried layer for preventing latch-up due to a parasitic thyristor,
Reference numeral 303 denotes an N ⁻ type epitaxial region, 304 denotes a P ⁺ type isolation / diffusion region, and 305 denotes an isolation oxide film. The P-type diffusion layer resistor 306 is formed by diffusing a P-type impurity into the P ⁺ -type isolation / diffusion region 304 and the N ⁻ -type epitaxial region 303 surrounded by the isolation / oxide film 305. At present, as a method for introducing a P-type impurity, an ion implantation method is generally used, and is significantly superior to a thermal diffusion method or the like in terms of precision and miniaturization. 307 is B
An interlayer insulating film such as PSG (borophosphosilicate glass), 30
8 is a contact hole, and 309 is a metal wiring such as aluminum.

[0003]

SUMMARY OF THE INVENTION In recent integrated circuits,
As the miniaturization progresses, the interlayer insulating film is becoming thinner. On the other hand, the power supply voltage is still the 5V system as usual, and there are still bipolar integrated circuits of the medium / high withstand voltage system such as the 12V system and the 40V system. Therefore, in the conventional structure of the diffusion layer resistor, for example, FIG.
When a power supply voltage is applied to the terminal B shown in FIG. 9A and the terminal C is connected to the ground, the surface of the N ⁻ -type epitaxial layer in the resistance forming region undergoes P-type inversion because the interlayer insulating film 307 is thin. There has been a problem that a leak current flows between the resistors.

In the prior art, in order to solve this problem, an insulating oxide film is provided between the resistors as shown in FIG. 4 so as to prevent surface inversion. Will be hindered.

An object of the present invention is to provide a semiconductor diffusion layer resistor for a semiconductor integrated circuit which can suppress a decrease in threshold voltage of a parasitic MOS transistor when an interlayer insulating film is thinned and can prevent a leak current. Is to do.

[0006]

According to the present invention, there is provided a semiconductor diffusion layer resistor comprising a first conductivity type insulating isolation region or a second conductivity type diffusion layer resistance forming region surrounded by an insulating oxide film;
A diffusion layer resistance region in which impurities of the conductivity type are diffused; and a impurity concentration higher than that of the diffusion layer resistance formation region of the second conductivity type .
A second conductivity type channel stopper layer having a shallower impurity depth and a lower impurity concentration than the diffusion layer resistance region in which the one conductivity type impurity is diffused is provided.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1A is a structural sectional view of a semiconductor diffusion layer resistor according to one embodiment of the present invention. 101 is a P ^- type semiconductor substrate, 10
2 is an N ⁻ type buried layer for preventing latch-up, 103 is an N ⁻ type epitaxial region, 104 is a P ⁻ type insulating isolation region, 1
Reference numeral 05 denotes an insulating isolation oxide film, and reference numeral 106 denotes a P-type diffusion resistance region . The above is the same as the conventional diffusion layer resistance shown in FIG.

A feature of the present invention resides in that an N ⁻ type channel stopper region 110 is provided. This channel stopper region has a shallower impurity depth than the resistance region 106 and a lower impurity concentration. 107 is an interlayer insulating film, 108
Is a contact hole, and 109 is a metal wiring layer. FIG.
(B) shows the depth profile of a-a ₁ cross section and b-b ₁ cross section in FIG. 1 (a). As can be seen from this profile, since the N-type channel stopper region was formed in the portion (bb- ₁ cross section) which was the conventional epitaxial region, the impurity concentration on the surface was high, and surface inversion was unlikely to occur. For example, the concentration of the epitaxial layer of the conventional example is 5 × 10 ¹⁵ cm ⁻³ , and the surface concentration of the N-type channel stopper region of the present invention is 1 × 10 ¹⁷ cm ⁻³ .
Assuming ⁻³ , the threshold voltage difference between the parasitic MOS transistors having the interlayer insulating films 107 and 307 as gate insulating films is about 35 V in theoretical value, which is higher in the present invention.

On the other hand, as you can see the profile of a-a ₁ section, the junction of the bottom surface portion of the P-type resistor, the impurity depth of the P-type resistor is deeper than the depth of the N-type channel stopper, a P-type The junction is formed between the resistance layer and the N ⁻ -type epitaxial layer. Although the junction capacitance slightly increases at the side surface of the resistance region, the junction capacitance can take the same value as the conventional one at the bottom surface. In addition, the resistance layer generally has a depth of 0.2 to
Since the width of the resistance layer is an order of magnitude higher than several μm, whereas the width is as short as 0.5 μm, the area ratio between the side surface and the bottom surface of the resistance region per unit length is 1:10 to 1:30. The increase in the parasitic capacitance on the side surface can be almost ignored. In recent high-speed devices, RC due to an increase in parasitic capacitance
Although an increase in the time constant poses a problem, in the present invention, the parasitic capacitance can be suppressed to substantially the same level as in the related art.

FIG. 2 shows the diffusion resistance of the technique related to the present invention.
It is sectional drawing which shows an example . Channel stopper layer of N-type in the embodiment of the present invention, while has been formed by introducing the impurity diffusion resistors forming the entire region, in the example of the related art,
The N-type channel stopper layer 210 is formed by selectively introducing an impurity between the resistors, so that the N-type channel stopper layer 210 and the P-type diffusion layer 204 are not directly joined. This was junction breakdown voltage is improved compared with the examples, but the area of the resistor forming region is specific base multi <br/> little increase to an embodiment of the present invention. However, the degree of the increase can be kept small as compared with the prior art using the insulating isolation oxide film.

[0011]

As described above, according to the present invention, the impurity concentration is lower and the impurity depth is lower in the second conductivity type region where the first conductivity type diffusion layer resistance is formed than in the first conductivity type resistance diffusion layer. By providing a shallow second-conductivity-type channel stopper layer, the threshold voltage of the parasitic MOS transistor can be prevented from lowering when the interlayer insulating film is thinned, and leakage current can be prevented. . Therefore, the metal wiring can be freely passed over the diffusion resistance forming region via the interlayer insulating film, and the degree of freedom in circuit design is improved.

Further, since the bottom surface of the resistance diffusion layer does not form a junction with the channel stopper layer, the junction capacitance can be suppressed to the same level as in the prior art, and does not hinder the speeding up of the integrated circuit.

[Brief description of the drawings]

Impurity profile of the resistive diffusion layer and the channel stopper layer in FIG. 1 of the semiconductor chip of an embodiment of the present invention cross-sectional view and its a-a ₁ and b-b _1.

FIG. 2 is a sectional view of a semiconductor chip according to another embodiment of the present invention.

Figure 3 is a schematic top view and A-A ₁ cross-sectional view of a conventional semiconductor diffusion layer resistance formation region.

FIG. 4 is a sectional view of a semiconductor chip showing a conventional technique for preventing a leak current between resistors.

[Explanation of symbols]

101, 201, 301, 401 P ⁻ type semiconductor substrate 102, 202, 302, 402 N ⁺ type buried layer 103, 203, 303, 403 N ⁻ type epitaxial region 104, 204, 304, 404 P ⁺ type isolation / diffusion region 105, 205, 305, 405 Insulation / isolation oxide film 106, 206, 306, 406 P-type diffusion resistance region 107, 207, 307, 407 Interlayer insulation film 108, 208, 308, 408 Contact hole 109, 209, 309, 409 Metal Wiring 110, 210 N-type channel stopper layer

Claims (2)

(57) [Claims] An impurity of a first conductivity type is diffused in a desired shape into a second conductivity type semiconductor diffusion layer resistance forming region surrounded by a first conductivity type insulation isolation region or a second conductivity type semiconductor diffusion layer. in semiconductor diffusion layer resistance, the semiconductor diffusion layer resistance formation region of the second conductivity type semiconductor diffusion of the second conductivity type
Although the impurity concentration is higher than that of the layer resistance forming region, the first
A semiconductor diffusion layer resistor comprising a channel stopper layer doped with a second conductivity type impurity having a lower concentration and a shallower impurity depth than a semiconductor diffusion layer resistance region formed by diffusing a conductivity type impurity. 2. The semiconductor diffusion layer resistance according to claim 1, wherein said channel stopper layer is formed by introducing an impurity into the entire surface of the semiconductor diffusion layer resistance formation region of the second conductivity type.